High-speed high-resolution ADC for precision measurements
First Claim
1. A measuring instrument comprising:
- a first Analog-to-Digital Converter (ADC) and a second ADC, wherein each of the first and the second ADC comprises an input and an output, wherein the first ADC and the second ADC are operable to convert analog data to digital data during a cycle;
wherein the first ADC is further operable to covert the analog data to the digital data and generate conversion results for the first ADC;
wherein the first ADC is further operable to generate an error signal; and
wherein the second ADC is further operable to sample the error signal, wherein said sampling occurs at a phase of the cycle when a rate of change of the error signal is independent of the conversion results for the first ADC;
wherein the first ADC comprises an internal feedback loop, wherein the internal feedback loop is operable to use return-to-zero coding.
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Abstract
A measurement device such as a DMM may include four basic units—an analog circuit path, an analog to digital converter (ADC), a digital filter, and an RMS computation unit. The four basic units may be operable to multiplex or to process one or more of the plurality of channels at the same time. The analog circuit path may include the necessary circuitry for the plurality of channels to couple to one or more analog signals. The analog circuit path may couple to the ADC. The ADC may be operable to receive the one or more analog signals from the analog circuit path and convert it to one or more digital signals. The ADC may include a cascaded ADC, which may include a first ADC and a second ADC. The first and the second ADC and may be able to convert analog data to digital data during a cycle. In one embodiment, the first ADC may generate a conversion result and an error signal. The second ADC may be operable to receive the error signal, digitize the error signal, and process the error signal, thus performing noise cancellation. A summation operation may combine the data from the first ADC and the processed data from the second ADC. The cascaded ADC may consist of a continuous-time 1-bit sigma-delta modulator followed by a SAR ADC. Digital output from sigma-delta modulator may be weighted and summed with the output of the SAR ADC in an FPGA.
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Citations
49 Claims
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1. A measuring instrument comprising:
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a first Analog-to-Digital Converter (ADC) and a second ADC, wherein each of the first and the second ADC comprises an input and an output, wherein the first ADC and the second ADC are operable to convert analog data to digital data during a cycle; wherein the first ADC is further operable to covert the analog data to the digital data and generate conversion results for the first ADC; wherein the first ADC is further operable to generate an error signal; and wherein the second ADC is further operable to sample the error signal, wherein said sampling occurs at a phase of the cycle when a rate of change of the error signal is independent of the conversion results for the first ADC; wherein the first ADC comprises an internal feedback loop, wherein the internal feedback loop is operable to use return-to-zero coding. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21)
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22. A high-precision DAC comprising:
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a first and a second DAC coupled together, wherein each of the first and the second DAC comprises an input and an output, wherein the output of the second DAC is coupled to the output of the first DAC, wherein the first DAC and the second DAC are each operable to generate and receive a load current, and wherein the load current seen by the first DAC is altered by a changing current load from the second DAC, wherein the load current received by the first DAC is substantially zero. - View Dependent Claims (23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34)
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35. A method for measuring analog data using a measuring instrument, the method comprising:
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converting the analog data to digital data during a cycle using a first ADC and a second ADC, wherein each of the first and the second ADC comprises an input and an output, wherein the first ADC is operable to covert the analog data to the digital data and generate conversion results for the first ADC; the first ADC generating an error signal; and the second ADC sampling the error signal, wherein said sampling occurs at a phase of the cycle when a rate of change of the error signal is independent of the conversion results for the first ADC; wherein the first ADC comprises an internal feedback loop, wherein the internal feedback loop is operable to use return-to-zero coding. - View Dependent Claims (36, 37, 38, 39, 40, 41)
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42. A measuring instrument comprising:
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a first Analog-to-Digital Converter (ADC) and a second ADC, wherein each of the first and the second ADC comprises an input and an output, wherein the first ADC and the second ADC are operable to convert analog data to digital data during a cycle;
wherein the first ADC is further operable to covert the analog data to the digital data and generate conversion results for the first ADC;wherein the first ADC is further operable to generate an error signal; and wherein the second ADC is further operable to sample the error signal, wherein said sampling occurs at a phase of the cycle when a rate of change of the error signal is independent of the conversion results for the first ADC; wherein the first ADC further comprises a sigma-delta modulator; wherein the first ADC further comprises a DAC comprising an input and an output; wherein the first ADC further comprises one or more integrators; and wherein the DAC comprises a first DAC and a second DAC coupled together, wherein each of the first DAC and the second DAC comprises an input and an output. - View Dependent Claims (43, 44, 45, 46, 47, 48)
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49. A measuring instrument comprising:
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a first Analog-to-Digital Converter (ADC) and a second ADC, wherein each of the first and the second ADC comprises an input and an output, wherein the first ADC and the second ADC are operable to convert analog data to digital data during a cycle;
wherein the first ADC is further operable to convert the analog data to the digital data and generate conversion results for the first ADC;wherein the first ADC is further operable to generate an error signal; and wherein the second ADC is further operable to sample the error signal, wherein said sampling occurs at a phase of the cycle when a rate of change of the error signal is independent of the conversion results for the first ADC; wherein the first ADC further comprises a sigma-delta modulator; wherein the first ADC further comprises a DAC comprising an input and an output; wherein the first ADC further comprises one or more integrators; and wherein the first ADC further comprises a first integrator and a second integrator, wherein each of the first integrator and the second integrator comprises an input and an output, and wherein the output of the DAC is coupled to the input of the first integrator.
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Specification