Variable capacitance switched capacitor input system and method

• US 6,970,126 B1
• Filed: 06/25/2004
• Issued: 11/29/2005
• Est. Priority Date: 06/25/2004
• Status: Active Grant

• Current Assignee: Analog Devices, Inc.
• Original Assignee: Analog Devices, Inc.
• Inventors: O'Dowd, John, McCartney, Damien
• Primary Examiner(s): Jeanglaude, Jean Bruner
• Application Number:
  US10/876,883
• Time in Patent Office: 522 Days
• Field of Search: 341/172, 341/143, 341/155, 341/139, 341/152, 375/247, 327/341, 324/678, 737/24
• US Class Current: 341/172
• CPC Class Codes: H03M 3/34 by chopping
• CPC Class Codes: H03M 3/43 the quantiser being a single bit one

Abstract

A variable capacitance switched capacitor input system and method includes a differential integrator circuit having first and second input summing nodes and a variable sensing capacitor; one terminal of the variable sensing capacitor is connected to one of the nodes in the first phase and to the other of the nodes in the second phase; an input terminal connected to a second terminal of the variable sensing capacitor receives a first voltage level in the first phase and a second voltage level in the second phase for delivering the charge on the variable sensing capacitor to the first summing node in the first phase and to the second summing node in the second phase and canceling errors in a differential integrator circuit output caused by leakage current.

Claims

1. A variable capacitance switched capacitor input system comprising:

a differential integrator circuit having first and second input summing nodes;

a variable sensing capacitor;

a switching system for connecting one terminal of said variable sensing capacitor to one of said nodes in a first phase and to the other of said nodes in a second phase; and

a second terminal of said variable sensing capacitor for receiving a first voltage level in said first phase and a second voltage level in said second phase for transferring the charge on said variable sensing capacitor to said first summing node in said first phase and to said second summing node in said second phase and canceling errors in the differential integrator circuit output caused by leakage current.

2. The variable capacitance switched capacitor input system of claim 1 in which said integrator circuit includes a reset circuit for periodically resetting said integrator circuit.

3. The variable capacitance switched capacitor input system of claim 1 further including a bilevel voltage source for providing said first and second voltage levels.

4. The variable capacitance switched capacitor input system of claim 1 in which said integrator circuit is in a sigma delta converter.

5. The variable capacitance switched capacitor input system of claim 1 further including

a reference capacitor,

a bilevel reference voltage source having first and second reference voltage levels and a second switching system

for connecting to a first terminal of said reference capacitor,

a first reference voltage level in a first state and

a second reference voltage level in a second state, and

for connecting the second terminal of said reference capacitor to one of said summing nodes in said first state, and the other of said summing nodes in said second state,

for transferring the reference capacitor charge to said integrator circuit in both states.

6. The variable capacitance switched capacitor input system of claim 1 in which said variable sensing capacitor is remote from said switching system and said integrator circuit.

7. The variable capacitance switched capacitor input system of claim 1 in which said variable sensing capacitor, said switching system and said integrator circuit are on a single chip.

8. The variable capacitance switched capacitor input system of claim 1 in which said first and second phases are of approximately equal duration.

9. The variable capacitance switched capacitor input system of claim 1 in which said differential integrator circuit includes two capacitors and they are approximately equal.

10. A variable capacitance switched capacitor input system comprising:

a differential integrator circuit having first and second input summing nodes;

first and second variable sensing capacitors;

first and second switching systems associated with said first and second variable sensing capacitors, respectively, each said switching system connecting one terminal of its associated variable sensing capacitor to one of said nodes in a first phase and to the other of said nodes in a second phase; and

each said variable sensing capacitor having a second terminal for receiving a first voltage level in said a first phase and a second voltage level in said second phase

for transferring the charge on the associated said variable sensing capacitor to said one summing node in said first phase and to the other summing node in said second phase

and canceling errors in each phase in the differential circuit output caused by leakage current.

11. The variable capacitance switched capacitor input of claim 10 in which each said switching system connects said one terminal of its associated variable sensing capacitor to the same one of said nodes in the first phase and to the same other of said nodes in the second phase.

12. The variable capacitance switched capacitor input of claim 10 in which each said switching system connects said one terminal of its associated variable sensing capacitor to a different one of said nodes in the first phase and swaps them to the other nodes in the second phase.

13. A variable capacitance switched capacitor input system comprising:

a differential integrator circuit having first and second input summing nodes;

first and second variable sensing capacitors;

first and second switching systems associated with said first and second variable sensing capacitors, respectively, each said switching system connecting one terminal of its associated variable sensing capacitor to one of said nodes in a first phase and to the other of said nodes in a second phase; and

each of said variable sensing capacitors having a shared second terminal for receiving

a first voltage level in said first phase and a second voltage level in said second phase

for transferring the charge on the associated said variable sensing capacitor to said one summing node in said first phase and to the other summing node in said second phase

and canceling errors in each phase in the differential circuit output caused by leakage current.

14. A variable capacitance switched capacitor sigma delta modulator system comprising:

a differential integration circuit having first and second input summing nodes;

a variable sensing capacitor;

a switching system for connecting one terminal of said variable sensing capacitor to one of said nodes in a first phase and to the other of said nodes in a second phase; and

a second terminal of said variable sensing capacitor for receiving a first voltage level in said first phase and a second voltage level in said second phase

for transferring the charge on said variable sensing capacitor to said first summing node in said first phase and to said second summing node in said second phase

and canceling errors in the differential integrator circuit output caused by leakage current.

15. A variable capacitance switched capacitor sigma delta modulator system comprising:

a differential integrator circuit having first and second input summing nodes;

first and second variable sensing capacitors;

first and second switching systems associated with said first and second variable sensing capacitors, respectively, each said switching system connecting one terminal of its associated variable sensing capacitor to one of said nodes in a first phase and to the other of said nodes in a second phase; and

each said variable sensing capacitor having a second terminal for receiving a first voltage level in said first phase and a second voltage level in said second phase

for transferring the charge on the associated said variable sensing capacitor to said one summing node in said first phase and to the other summing node in said second phase

and canceling errors in each phase in the differential circuit output caused by leakage current.

16. The variable capacitance switched capacitor sigma delta modulator system of claim 15 in which each said switching system connects said one terminal of its associated variable sensing capacitor to the same one of said nodes in the first phase and to the same other of said nodes in the second phase.

17. The variable capacitance switched capacitor sigma delta modulator system of claim 15 in which each said switching system connects said one terminal of its associated variable sensing capacitor to a different one of said nodes in the first phase and swaps them to the other nodes in the second phase.

18. A variable capacitance switched capacitor sigma delta modulator system comprising:

a differential integrator circuit having first and second input summing nodes;

first and second variable sensing capacitors;

first and second switching systems associated with said first and second variable sensing capacitors, respectively, each said switching system connecting one terminal of its associated variable sensing capacitor to one of said nodes in a first phase and to the other of said nodes in a second phase; and

each of said variable sensing capacitors having a shared second terminal for receiving

a first voltage level in said first phase and a second voltage level in said second phase

for transferring the charge on the associated said variable sensing capacitor to said one summing node in said first phase and to the other summing node in said second phase

and canceling in each phase in the differential circuit output caused by leakage current.

19. A switching method for a variable capacitance switched capacitor input system having a differential integrator circuit having first and second input summing nodes, a variable sensing capacitor and second terminal of said variable sensing capacitor comprising:

connecting one terminal of said variable sensing capacitor to one of said summing nodes in a first phase and to the other of said summing nodes in a second phase; and

applying to said second terminal of said variable capacitor

a first voltage level in said first phase and a second voltage level in said second phase

for transferring the charge on said variable sensing capacitor to said first summing node in said first phase and to said second summing node in said second phase

and canceling errors in the differential integrator circuit output caused by leakage current.