Circuit and system for extracting data

• US 6,970,521 B2
• Filed: 12/21/2000
• Issued: 11/29/2005
• Est. Priority Date: 12/24/1999
• Status: Expired due to Fees

• Current Assignee: Matsushita Electric Industrial Company Limited (Panasonic Holdings Corporation)
• Original Assignee: Matsushita Electric Industrial Company Limited (Panasonic Holdings Corporation)
• Inventors: Dosho, Shiro
• Primary Examiner(s): Le, Amanda T.
• Assistant Examiner(s): Ware, Cicely
• Application Number:
  US09/741,086
• Publication Number:
  US 20010005156A1
• Time in Patent Office: 1,804 Days
• Field of Search: 375/340, 375/354, 375371-373, 327/291, 327152-261, 348/537
• US Class Current: 375/340
• CPC Class Codes: H04L 7/0025 interpolation of clock signal
• CPC Class Codes: H04L 7/0338 the correction of the phase error being performed by a feed forward loop

Abstract

A data extracting circuit extracts data much more accurately at a much higher response speed. A clock transfer section propagates an input clock signal through unit delay devices thereof. An edge detecting section locates an edge of the clock signal, which edge is being propagated through the clock transfer section, for a time represented by a given edge of an input data signal. In response to an edge detection signal indicating the clock signal edge located, a clock selecting section selects one of outputs of the delay devices, and presents the output as a clock input to a latch.

Claims

1. A data extracting circuit comprising:

a clock transfer section, including multiple unit delay devices connected in series together, for propagating an input clock signal through the delay devices;

an edge detecting section for locating an edge of the clock signal, which edge is being propagated through the clock transfer section, for a time represented by a given edge of an input data signal, and for outputting an edge detection signal indicating the clock signal edge located;

a clock selecting section for selecting one of outputs of the delay devices responsive to the edge detection signal; and

a latch for receiving the output, selected by the selecting section, and the data signal as clock and data inputs, respectively, and for outputting read data;

wherein the selecting section comprises;

multiple switches provided for the respective delay devices, each said switch selectively delivering the output of associated one of the delay devices responsive to the edge detection signal; and

an OR gate tree, in which a plurality of OR gates are connected together like a tree and which receives outputs of the switches.

2. A data extracting circuit comprising:

a clock transfer section, including multiple unit delay devices connected in series together, for propagating an input clock signal through the delay devices;

an edge detecting section for locating an edge of the clock signal, which edge is being propagated through the clock transfer section, for a time represented by a given edge of an input data signal, and for outputting an edge detection signal indicating the clock signal edge located;

a clock selecting section for selecting one of outputs of the delay devices responsive to the edge detection signal; and

a latch for receiving the output, selected by the selecting section, and the data signal as clock and data inputs, respectively, and for outputting read data;

wherein the selecting section comprises multiple interpolators, each said interpolator obtaining an interpolated signal from the output and input of associated one of the delay devices, and selects one of the interpolated signals obtained by the interpolators.

3. A data extracting circuit comprising:

a clock transfer section, including multiple unit delay devices connected in series together, for propagating an input clock signal through the delay devices;

an edge detecting section for locating an edge of the clock signal, which edge is being propagated through the clock transfer section, for a time represented by a given edge of an input data signal, and for outputting an edge detection signal indicating the clock signal edge located;

a first group of switches provided for the respective delay devices, each said switch of the first group selectively delivering the output of associated one of the delay devices responsive to the edge detection signal;

a selected clock transfer section including multiple unit transfer gates that are connected in series together and that receive the outputs of the respective switches of the first group;

a first data transfer section, including multiple unit transfer gates connected in series together, for propagating the input data signal through the transfer gates thereof;

a second group of switches provided for the respective transfer gates of the first data transfer section, each said switch of the second group selecting the output of associated one of the transfer gates responsive to the edge detection signal;

a second data transfer section, including multiple unit transfer gates that are connected in series together and that receive the outputs of the respective switches of the second group; and

a latch for receiving an output of the second data transfer section and an output of the selected clock transfer section as data and clock inputs, respectively, and for outputting read data.

4. The circuit of claim 3, wherein the transfer gates of the first and second data transfer sections have the same configuration as the transfer gates of the selected clock transfer section.

5. The circuit of claim 3, further comprising first delay means for delaying the output of the selected clock transfer section for a predetermined amount of time and then delivering the delayed output to the latch.

6. The circuit of claim 3, further comprising second delay means, provided for the switches of the second group, for delaying the outputs of the transfer gates of the first data transfer section for a predetermined amount of time.

7. The circuit of claim 3, further comprising multiple interpolators, each said interpolator obtaining an interpolated signal from the output and input of associated one of the delay devices of the clock transfer section, wherein each said switch of the first group selects associated one of the interpolated signals obtained by the interpolators.

8. The circuit of claim 3, which uses a clock signal, generated by a PLL circuit, as the input clock signal.

9. The circuit of claim 3, which uses a clock signal, generated by a quartz oscillator, as the input clock signal.

10. A data extracting system comprising:

a data extracting circuit according to claim 3;

a PLL circuit that receives the data signal, which is also input to the data extracting circuit, and that generates and delivers the clock signal to the data extracting circuit;

a FIFO memory that receives the read data and a read clock signal, which have been output from the data extracting circuit, as its input data and input clock signal, respectively; and

read enabling means for monitoring a phase locking state of the PLL circuit and for delivering the clock signal, which has been generated by the PLL circuit, as an output clock signal to the FIFO memory when the PLL circuit accomplishes the phase locking.

11. A data extracting system comprising:

a data extracting circuit according to claim 3;

a quartz oscillator that generates and delivers the clock signal to the data extracting circuit;

a FIFO memory that receives the read data and a read clock signal, which have been output from the data extracting circuit, as its input data and input clock signal, respectively; and

read enabling means for counting the number of pulses of the clock signal generated by the quartz oscillator and for delivering the clock signal, generated by the quartz oscillator, as an output clock signal to the FIFO memory when the count reaches a predetermined number.