Unified digital architecture

• US 6,970,529 B2
• Filed: 11/28/2001
• Issued: 11/29/2005
• Est. Priority Date: 01/16/2001
• Status: Expired due to Fees

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Cranford, Hayden Clavie Jr., Schmatz, Martin Leo, Norman, Vernon Roberts
• Primary Examiner(s): Patel, Jay K.
• Assistant Examiner(s): GHULAMALI, QUTBUDDIN
• Application Number:
  US09/996,113
• Publication Number:
  US 20020094055A1
• Time in Patent Office: 1,462 Days
• Field of Search: 375/376, 375/377, 375/371, 375/327, 375/354, 375/362, 375/374, 375/375, 375/328, 327/156, 327/157, 327/147
• US Class Current: 375/376
• CPC Class Codes: H03L 7/08 Details of the phase-locked loop
• CPC Class Codes: H03L 7/095 using a lock detector H03L7/087 takes precedence
• CPC Class Codes: H03L 7/0995 the oscillator comprising a ring oscillator
• CPC Class Codes: H03L 7/113 using frequency discriminator
• CPC Class Codes: H04L 2027/0067 Phase error detectors
• CPC Class Codes: H04L 7/0337 Selecting between two or more discretely delayed clocks or selecting between two or more discretely delayed received code signals

Abstract

A unified, unidirectional serial link is described for providing data across wired media, such as a chip-to chip or a card-to-card interconnect. It consists of a transmit section and a receive section that are operated as pairs to allow the serial data communication. The serial link is implemented as part of a VLSI ASIC module and derives its power, data and clocking requirements from the host modules. The logic transmitter portion contains a phase locked loop (PLL), a dibit data register, a finite impulse response (FIR) filter and a transmit data register. The phase locked loop comprises both a digital coarse loop and an analog fine loop. The digital receiver portion contains a PLL, an FIR phase rotator, a phase rotator control state machine, and a clock buffer. The transmitter and the receiver each preferably utilize a pseudo-random bit stream (PRBS) generator and checker.

Claims

1. A unified system for transmitting and receiving data by a serial link across wired media, and comprising a transmitter and a receiver, the transmitter comprising:

a) phase locked loop control circuit having a digital coarse loop and an analog fine loop, the coarse loop including a reference generator, a voltage comparator, a PLL control logic, a digital to analog counter and a low pass filter;

b) a two-stage voltage regulated ring oscillator controlled by the phase locked loop,

and capable of running at full bit frequency;

c) a frequency reference operating at one-fourth of full data rate;

d) a reference clock and a phase locked loop clock;

the fine loop control formed by a 4x frequency divider, a phase-frequency detector, a charge pump and a loop file; and

the receiver comprising a phase locked loop including a voltage controlled oscillator, a phase rotator independent of the phase locked loop and adapted to receive the output phases of the oscillator, a phase rotator control state machine for controlling the phase setting of a phase rotator and employing an over sampled half-rate system using a digitized early-late control.

2. The unified system according to claim 1, wherein the transmitter and the receiver each includes a pseudo random bit stream generator and checker for self testing.

3. The system according to claim 2 wherein the transmitter architecture is supported by three analog blocks comprising the full data rate PLL, a phase buffer to repower the PLL signal for the driver and an off chip driver with a pre-emphasis equalization.