Reducing tester channels for high pinout integrated circuits
First Claim
Patent Images
1. An integrated circuit comprising:
- a plurality of input pads configured to receive a plurality of first input signals;
an input circuit configured to generate a plurality of second input signals (i) equal to said first input signals while in an operational mode and (ii) responsive to a plurality of test vectors with timing generation determined by said first input signals while in a test mode, wherein said input circuit comprises a data formatter configured to generate said second input signals in response to said first input signals and a plurality of test signals conveying said test vectors; and
a core circuit configured to (i) directly receive said second input signals and (ii) respond to said second input signals.
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Abstract
An integrated circuit generally comprising a plurality of input pads, an input circuit, and a core circuit. The input pads may be configured to receive a plurality of first input signals. The input circuit may be configured to generate a plurality of second input signals (i) equal to the first input signals while in an operational mode and (ii) responsive to a plurality of test vectors with timing generation determined by the first signals while in a test mode. The core circuit may be responsive to the second input signals.
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Citations
19 Claims
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1. An integrated circuit comprising:
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a plurality of input pads configured to receive a plurality of first input signals; an input circuit configured to generate a plurality of second input signals (i) equal to said first input signals while in an operational mode and (ii) responsive to a plurality of test vectors with timing generation determined by said first input signals while in a test mode, wherein said input circuit comprises a data formatter configured to generate said second input signals in response to said first input signals and a plurality of test signals conveying said test vectors; and a core circuit configured to (i) directly receive said second input signals and (ii) respond to said second input signals. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10)
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11. An integrated circuit comprising:
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a core circuit configured to generate a plurality of first output signals; an output circuit configured to (i) generate a plurality of second output signals equal to said first output signals while in an operational mode and (ii) generate one of said second output signals in place of one of said first output signals in response to a comparison result of data in said first output signals to a plurality of test vectors while in a test mode; and a plurality of output pads configured to receive said second output signals. - View Dependent Claims (12, 13, 14, 15, 16, 17, 18)
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19. An integrated circuit comprising:
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means for receiving a plurality of first input signals using a plurality of input pads; means for generating a plurality of second input signals (i) equal to said first input signals while in an operational mode and (ii) responsive to a plurality of test vectors with timing generation of said second input signals determined by said first signals while in a test mode, wherein said means for generating a plurality of second input signals comprises a data formatter configured to generate said second input signals in response to said first input signals and a plurality of test signals conveying said test vectors; and means responsive to said second input signals using a core circuit configured to directly receive said second input signals.
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Specification