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Reducing tester channels for high pinout integrated circuits

  • US 6,971,045 B1
  • Filed: 05/20/2002
  • Issued: 11/29/2005
  • Est. Priority Date: 05/20/2002
  • Status: Active Grant
First Claim
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1. An integrated circuit comprising:

  • a plurality of input pads configured to receive a plurality of first input signals;

    an input circuit configured to generate a plurality of second input signals (i) equal to said first input signals while in an operational mode and (ii) responsive to a plurality of test vectors with timing generation determined by said first input signals while in a test mode, wherein said input circuit comprises a data formatter configured to generate said second input signals in response to said first input signals and a plurality of test signals conveying said test vectors; and

    a core circuit configured to (i) directly receive said second input signals and (ii) respond to said second input signals.

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