Thin-film semiconductor device and method of manufacturing the same

• US 6,972,215 B2
• Filed: 10/20/2003
• Issued: 12/06/2005
• Est. Priority Date: 01/31/2001
• Status: Expired due to Fees

• Current Assignee: Canon Kabushiki Kaisha (Canon Inc.)
• Original Assignee: Canon Kabushiki Kaisha (Canon Inc.)
• Inventors: Sakaguchi, Kiyofumi, Yonehara, Takao
• Primary Examiner(s): Pham, Long
• Assistant Examiner(s): Le, Thao X.
• Application Number:
  US10/687,743
• Publication Number:
  US 20040082149A1
• Time in Patent Office: 778 Days
• Field of Search: 438460-465, 438113-114, 438479-481, 438/311, 438/910, 257/620
• US Class Current: 438/113
• CPC Class Codes: H01L 21/02203 the layer being porous
• CPC Class Codes: H01L 21/02238 silicon in uncombined form, i.e. pure silicon
• CPC Class Codes: H01L 21/02255 formation by thermal treatment H01L21/02252 takes precedence; after treatment of an insulating film H01L21/3105 and subgroups
• CPC Class Codes: H01L 21/02307 treatment by exposure to a liquid
• CPC Class Codes: H01L 21/02337 treatment by exposure to a gas or vapour
• CPC Class Codes: H01L 21/304 Mechanical treatment, e.g. grinding, polishing, cutting H01L21/30625 takes precedence
• CPC Class Codes: H01L 21/306 Chemical or electrical treatment, e.g. electrolytic etching to form insulating layers H01L21/31
• CPC Class Codes: H01L 21/3063 Electrolytic etching
• CPC Class Codes: H01L 21/31675 of silicon
• CPC Class Codes: H01L 21/78 with subsequent division of the substrate into plural individual devices cutting to change the surface-physical characteristics or shape of semiconductor bodies H01L21/304
• CPC Class Codes: H01L 2221/68363 used in a transfer process involving transfer directly from an origin substrate to a target substrate without use of an intermediate handle substrate
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01067 Holmium [Ho]
• CPC Class Codes: H01L 2924/10253 Silicon [Si]
• CPC Class Codes: H01L 2924/1305 Bipolar Junction Transistor [BJT]

Abstract

A semiconductor device is manufactured using the method including the steps of anodizing a semiconductor substrate to form a porous semiconductor layer on a semiconductor region of the semiconductor substrate; forming a non-porous semiconductor layer on the porous semiconductor layer; forming a semiconductor element and/or semiconductor integrated circuit in the non-porous semiconductor layer; forming kerfs from a surface side of the non-porous semiconductor layer toward the semiconductor region; and applying a pressure of a fluid to the porous semiconductor layer such that the desired region of the semiconductor element and/or semiconductor integrated circuit is separated from the semiconductor substrate.

Claims

1. A method of manufacturing a semiconductor device, the method comprising:

anodizing a semiconductor substrate to form a porous semiconductor layer on a semiconductor region of the semiconductor substrate;

forming a non-porous semiconductor layer on the porous semiconductor layer;

forming a semiconductor element and/or semiconductor integrated circuit in the non-porous semiconductor layer;

forming kerfs from a surface side of the non-porous semiconductor layer toward the semiconductor region; and

applying a pressure of a fluid to the porous semiconductor layer such that a desired region of the semiconductor element and/or semiconductor integrated circuit is separated from the semiconductor substrate,

wherein the separation of the desired region is performed by injecting high-pressure fluid through the kerfs into the porous semiconductor layer.

2. The method according to claim 1, wherein the semiconductor substrate is a single-crystal silicon substrate or a compound semiconductor substrate.

3. The method according to claim 1, wherein the porous semiconductor layer comprises a plurality of layers having different porosities.

4. The method according to claim 3, wherein the porous semiconductor layer comprises a first porous semiconductor layer having a first porosity and a second porous semiconductor layer having a second porosity less than the first porosity, and wherein the first porous semiconductor layer and the second porous semiconductor layer are arranged in that order in a direction from the semiconductor region to the non-porous semiconductor layer.

5. The method according to claim 4, wherein the non-porous semiconductor layer is formed on the second porous semiconductor layer.

6. The method according to claim 5, wherein the plurality of layers having different porosities are formed by changing a density of current in the anodizing step.

7. The method according to claim 1, further comprising forming a protective film on inner walls of pores in the porous semiconductor layer.

8. The method according to claim 1, wherein the non-porous semiconductor layer is a single-crystal silicon layer or a compound semiconductor layer.

9. The method according to claim 1, wherein the non-porous semiconductor layer is a single-crystal silicon layer or a compound semiconductor layer.

10. The method according to claim 1, wherein the kerfs are formed by any one of dicing, etching, laser abrasion, ultrasonic cutter and high-pressure jet.

11. The method according to claim 1, wherein the kerfs are formed such that bottom portions of the kerfs are located in the porous semiconductor layer or at an interface between the non-porous semiconductor layer and the porous semiconductor layer.

12. The method according to claim 1, wherein the semiconductor element and/or semiconductor integrated circuit comprises any one of CMOS, bipolar transistor, diode, coil, capacitor, DRAM, microprocessor, logic IC and memory.