Manufacturing a conformal atomic liner layer in an integrated circuit interconnect

• US 6,972,254 B1
• Filed: 12/20/2002
• Issued: 12/06/2005
• Est. Priority Date: 06/01/2001
• Status: Expired due to Fees

• Current Assignee: GlobalFoundries, Inc.
• Original Assignee: Advanced Micro Devices, Inc.
• Inventors: Ngo, Minh Van, Lopatin, Sergey D.
• Primary Examiner(s): Weiss, Howard
• Application Number:
  US10/327,428
• Time in Patent Office: 1,082 Days
• Field of Search: 438/627, 438/637, 438/656
• US Class Current: 438/637
• CPC Class Codes: H01L 21/28562 Selective deposition
• CPC Class Codes: H01L 21/7681 involving one or more buried masks
• CPC Class Codes: H01L 21/76814 post-treatment or after-treatment, e.g. cleaning or removal of oxides on underlying conductors
• CPC Class Codes: H01L 21/76838 characterised by the formation and the after-treatment of the conductors etching for patterning the conductors H01L21/3213
• CPC Class Codes: H01L 21/76843 formed in openings in a dielectric
• CPC Class Codes: H01L 21/76844 Bottomless liners
• CPC Class Codes: H01L 21/76862 Bombardment with particles, e.g. treatment in noble gas plasmas; UV irradiation
• CPC Class Codes: H01L 21/76865 Selective removal of parts of the layer H01L21/76844 takes precedence
• CPC Class Codes: H01L 21/76876 for deposition from the gas phase, e.g. CVD
• CPC Class Codes: H01L 23/5226 Via connections in a multilevel interconnection structure
• CPC Class Codes: H01L 23/53238 Additional layers associated with copper layers, e.g. adhesion, barrier, cladding layers
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

A manufacturing method for an integrated circuit has a substrate with a semiconductor device thereon. A channel dielectric layer is deposited over the device and has an opening provided therein. A reducing process is performed in order to reduce the oxidation on the conductor and a conformal atomic liner is deposited in an atomic layer thickness to line the opening in the channel dielectric layer. A barrier layer is deposited over the conformal atomic liner and a seed layer is deposited over the barrier layer. A conductor core layer is deposited on the seed layer, filling the opening over the barrier layer and connecting to the semiconductor device.

Claims

1. A method of manufacturing an integrated circuit comprising;

providing a substrate having a semiconductor device thereon and an oxidizable conductor connected thereto;

forming a dielectric layer over the substrate and the oxidizable conductor;

forming an opening in the dielectric layer exposing the oxidizable conductor;

applying a reducing process to the opening in the dielectric layer to reduce the oxidizable conductor;

depositing a conformal atomic liner over the dielectric layer and lining the opening to an atomic layer thickness;

depositing a barrier layer over the conformal atomic liner;

depositing a conductor core layer over the barrier layer to fill the opening in the dielectric layer.

2. The method of manufacturing an integrated circuit as claimed in claim 1 wherein depositing the conformal atomic liner deposits a material selected from a group consisting of titanium, tantalum, tungsten, an alloy thereof, and a compound thereof.

3. The method of manufacturing an integrated circuit as claimed in claim 1 wherein depositing the conformal atomic liner deposits a material selected from a group consisting of titanium, tantalum, tungsten, an alloy thereof, and a compound thereof and the material includes impurities selected from a group consisting of nitrogen, silicon, and carbon.

4. The method of manufacturing an integrated circuit as claimed in claim 1 wherein depositing the conformal atomic liner deposits multiple atomic layer thicknesses of a material selected from a group consisting of titanium, tantalum, tungsten, an alloy thereof, and a compound thereof.

5. The method of manufacturing an integrated circuit as claimed in claim 1 including amorphizing the conformal atomic liner.

6. The method of manufacturing an integrated circuit as claimed in claim 1 wherein depositing the barrier layer deposits a material selected from a group consisting of titanium, tantalum, tungsten, an alloy thereof, and a compound thereof.

7. The method of manufacturing an integrated circuit as claimed in claim 1 wherein depositing the conformal atomic liner deposits an atomic layer thickness of material from 30 to 70 angstroms thick.

8. The method of manufacturing an integrated circuit as claimed in claim 1 wherein depositing the conformal atomic liner is performed using a process selected from the group consisting of atomic layer deposition, atomic layer chemical vapor deposition, and a combination thereof.

9. The method of manufacturing an integrated circuit as claimed in claim 1 including applying a plasma reduction process before depositing the conformal atomic layer deposition.

10. The method of manufacturing an integrated circuit as claimed in claim 1 wherein depositing the barrier layer is performed using a process selected from the group consisting of chemical-vapor deposition, self-ionized plasma deposition, and a combination thereof.

11. The method of manufacturing an integrated circuit as claimed in claim 1 including increasing the atomic layer thickness of the conformal atomic liner by a sputtering process.

12. The method of manufacturing an integrated circuit as claimed in claim 1 wherein depositing the conductor core deposits material selected from a group consisting of copper, gold, silver, a compound thereof, and a combination thereof.

13. The method of manufacturing an integrated circuit as claimed in claim 1 wherein depositing the dielectric layer deposit a material having a dielectric constant under 3.9.

14. The method of manufacturing an integrated circuit as claimed in claim 1 including depositing a seed layer on the barrier layer and depositing the seed layer deposits material selected from a group consisting of copper, gold, silver, a compound thereof, and a combination thereof.