Fabricating a tapered hole incorporating a resinous silicon containing film

• US 6,972,263 B2
• Filed: 04/08/2004
• Issued: 12/06/2005
• Est. Priority Date: 11/27/1995
• Status: Expired due to Fees

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: Fukunaga, Takeshi, Yamazaki, Shunpei
• Primary Examiner(s): Coleman, W. David
• Application Number:
  US10/819,964
• Publication Number:
  US 20040192025A1
• Time in Patent Office: 607 Days
• Field of Search: 438/453, 438/639, 438/712, 438/713, 738/725
• US Class Current: 438/713
• CPC Class Codes: H01J 2217/49 Display panels, e.g. not making use of alternating current H01J2211/10 takes precedence
• CPC Class Codes: H01L 23/5222 Capacitive arrangements or effects of, or between wiring layers other capacitive arrangements H01L23/642
• CPC Class Codes: H01L 23/5226 Via connections in a multilevel interconnection structure
• CPC Class Codes: H01L 23/5329 Insulating materials
• CPC Class Codes: H01L 27/124 with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits wiring structures per se H01L23/52
• CPC Class Codes: H01L 27/1244 for preventing breakage, peeling or short circuiting
• CPC Class Codes: H01L 27/1248 with a particular composition or shape of the interlayer dielectric specially adapted to the circuit arrangement
• CPC Class Codes: H01L 29/78621 with LDD structure or an extension or an offset region or characterised by the doping profile
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

A semiconductor device having reliable electrode contacts. First, an interlayer dielectric film is formed from a resinous material. Then, window holes are formed. The interlayer dielectric film is recessed by oxygen plasma. This gives rise to tapering window holes. This makes it easy to make contacts even if the circuit pattern is complex.

Claims

1. A method of fabricating a semiconductor device comprising:

forming a first dielectric film containing silicon;

forming a second dielectric film from a resinous material over said first dielectric film;

wherein a contact hole is provided in said first dielectric film and said second dielectric film before an isotropic etching is conducted to widen an opening of said contact hole, and

wherein selectivity of said second dielectric film with respect to said first dielectric film is 5 or more in said isotropic etching.

2. A method according to claim 1 wherein said first dielectric film comprises a material selected from the group consisting of silicon oxide, silicon nitride and silicon oxynitride.

3. A method according to claim 1 wherein said first dielectric film is formed after forming a semiconductor film comprising a source region and a drain region and a channel region and after forming a gate insulating film and after forming a gate electrode.

4. A method according to claim 1 wherein said second dielectric film comprises polyimide.

5. A method according to claim 3 further comprising crystallizing said semiconductor film.

6. A method according to claim 1 wherein said isotropical etching is conducted by using plasma.

7. A method of fabricating a semiconductor device comprising:

forming a first dielectric film containing silicon;

forming a second dielectric film from a resinous material over said first dielectric film;

wherein a contact hole is provided in said first dielectric film and said second dielectric film before an isotropic etching is conducted through a mask comprising a metal provided over said second dielectric film to widen an opening of said contact hole, and

wherein selectivity of said second dielectric film with respect to said first dielectric film is 5 or more in said isotropic etching.

8. A method according to claim 7 wherein said first dielectric film comprises a material selected from the group consisting of silicon oxide, silicon nitride and silicon oxynitride.

9. A method according to claim 7 wherein said first dielectric film is formed after forming a semiconductor film comprising a source region and a drain region and a channel region and after forming a gate insulating film and after forming a gate electrode.

10. A method according to claim 7 wherein said mask comprises titanium.

11. A method according to claim 7 wherein said mask comprises indium tin oxide.

12. A method according to claim 7 wherein said isotropic etching is conducted by using plasma.

13. A method according to claim 9 further comprising crystallizing said semiconductor film.