Integrated circuit and method for its manufacture

• US 6,972,478 B1
• Filed: 03/07/2005
• Issued: 12/06/2005
• Est. Priority Date: 03/07/2005
• Status: Expired due to Fees

• Current Assignee: GlobalFoundries, Inc.
• Original Assignee: Advanced Micro Devices, Inc.
• Inventors: Luning, Scott, Waite, Andrew M.
• Primary Examiner(s): Flynn, Nathan J.
• Assistant Examiner(s): QUINTO, KEVIN V
• Application Number:
  US11/075,774
• Time in Patent Office: 274 Days
• Field of Search: 257/347, 257/348, 257/349, 257/350, 257/351, 257/352, 257/353, 257/354, 257/627, 257/628, 257/618, 257/521, 257/527, 438/149, 438/478, 438/479, 438/480, 438/481, 438/150, 438/151, 438/152, 438/153, 438/154, 438/155, 438/156, 438/157, 438/158, 438/159, 438/160, 438/161, 438/162, 438/163, 438/164, 438/165, 438/166, 438/222, 438/226, 438/341
• US Class Current: 257/627
• CPC Class Codes: H01L 21/2007 Bonding of semiconductor wafers to insulating substrates or to semiconducting substrates using an intermediate insulating layer H01L21/2011 takes precedence; bonding of semiconductor wafers to semiconductor wafers for junction formation H01L21/187
• CPC Class Codes: H01L 21/823807 with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
• CPC Class Codes: H01L 21/84 the substrate being other than a semiconductor body, e.g. being an insulating body
• CPC Class Codes: H01L 27/1203 the substrate comprising an insulating body on a semiconductor body, e.g. SOI three-dimensional layout H01L27/0688
• CPC Class Codes: H01L 27/1207 combined with devices in contact with the semiconductor body, i.e. bulk/SOI hybrid circuits
• CPC Class Codes: H01L 29/045 by their particular orientation of crystalline planes
• CPC Class Codes: H01L 29/7833 with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's for thin film transistors H01L29/78618

Abstract

An integrated circuit and methods for its manufacture are provided. The integrated circuit comprises a bulk silicon substrate having a first region of <100> crystalline orientation and a second region of <110> crystalline orientation. A layer of silicon on insulator overlies a portion of the bulk silicon substrate. At least one field effect transistor is formed in the layer of silicon on insulator, at least one P-channel field effect transistor is formed in the second region of <110> crystalline orientation, and at least one N-channel field effect transistor is formed in the first region of <100> crystalline orientation.

Claims

1. An integrated circuit comprising:

a bulk silicon substrate comprising a first region having <

100>

orientation, and a second region having <

110>

orientation;

a layer of silicon on insulator overlying a portion of the bulk silicon substrate;

at least one field effect transistor formed in the layer of silicon on insulator;

at least one P-channel field effect transistor formed in the second region; and

at least one N-channel field effect transistor formed in the first region.

2. The integrated circuit of claim 1 wherein the at least one field effect transistor formed in the layer of silicon on insulator comprises at least one N-channel field effect transistor and at least one P-channel field effect transistor.

3. The integrated circuit of claim 1 wherein the first region comprises a P-type impurity doped region formed on the silicon substrate and the second region comprises an N-type impurity doped region formed on a silicon layer bonded to the silicon substrate.

4. The integrated circuit of claim 1 wherein the second region comprises an N-type impurity doped region formed on the silicon substrate and the first region comprises a P-type impurity doped region formed on a silicon layer bonded to the silicon substrate.

5. An integrated circuit comprising:

a silicon substrate having a first crystalline orientation;

a first silicon layer having a second crystalline orientation different than the first crystalline orientation bonded to the silicon substrate, the first silicon layer having an upper surface;

an insulator layer on the upper surface of the first silicon layer;

a second silicon layer on the insulator layer;

a first region of first crystalline orientation grown on the silicon substrate;

a second region of second crystalline orientation grown on the first silicon layer;

a first field effect transistor of first channel conductivity type formed in the first region;

a second field effect transistor of second channel conductivity type formed in the second region; and

complementary field effect transistors formed in the second silicon layer.

6. The integrated circuit of claim 5 wherein the first crystalline orientation comprises <

110>

crystalline orientation and the second crystalline orientation comprises <

100>

crystalline orientation.

7. The integrated circuit of claim 6 wherein the first region is impurity doped N-type and the first field effect transistor is a P-channel transistor.

8. The integrated circuit of claim 5 wherein the first crystalline orientation comprises <

100>

crystalline orientation and the second crystalline orientation comprises <

110>

crystalline orientation.

9. The integrated circuit of claim 8 wherein the second region is impurity doped N-type and the second field effect transistor is a P-channel transistor.

10. An integrated circuit comprising:

a silicon substrate having a first crystalline orientation;

a first silicon layer having a second crystalline orientation different than the first crystalline orientation bonded to the silicon substrate;

a layer of silicon on insulator overlying a portion of the silicon substrate and having an upper surface;

a first region of silicon having the first crystalline orientation grown on a portion of the silicon substrate and having a first upper surface;

a second region of silicon having the second crystalline orientation grown on a portion of the first silicon layer and having a second upper surface, the upper surface, the first upper surface, and the second upper surface all substantially coplanar;

a doped region of first conductivity type formed in the first region;

a doped region of second conductivity type formed in the second region;

a first field effect transistor of second channel conductivity type formed on the first region;

a second field effect transistor of first channel conductivity type formed on the second region;

complementary field effect transistors formed in the second silicon layer; and

electrical isolation regions formed between the first field effect transistor and the second field effect transistor and between the complementary field effect transistors and the first and second field effect transistors.

11. A method for manufacturing an integrated circuit comprising the steps of:

providing a silicon substrate having a first crystalline orientation;

bonding a silicon layer having a second crystalline orientation to the silicon substrate, the second crystalline orientation being different than the first crystalline orientation;

forming a silicon on insulator layer overlying the silicon layer;

etching through the silicon on insulator layer and the silicon layer to expose a portion of the silicon substrate;

etching through the silicon on insulator layer to expose a portion of the silicon layer;

growing a first selective epitaxial layer on the exposed portion of the silicon substrate;

growing a second selective epitaxial layer on the exposed portion of the silicon layer; and

forming a first field effect transistor in the first selective epitaxial layer, a second field effect transistor in the second selective epitaxial layer, and a third field effect transistor in the silicon on insulator layer.

12. The method of claim 11 wherein the step of providing a silicon substrate having a first crystalline orientation comprises the step of providing a silicon substrate having a <

100>

crystalline orientation and wherein the step of bonding a silicon layer having a second crystalline orientation comprises the step of bonding a silicon layer having a <

110>

crystalline orientation.

13. The method of claim 12 further comprising the steps of impurity doping first epitaxial layer P-type and impurity doping the second epitaxial layer N-type.

14. The method of claim 11 wherein the step of providing a silicon substrate having a first crystalline orientation comprises the step of providing a silicon substrate having a <

110>

crystalline orientation and wherein the step of bonding a silicon layer having a second crystalline orientation comprises the step of bonding a silicon layer having a <

100>

crystalline orientation.

15. The method of claim 12 further comprising the steps of impurity doping the first epitaxial layer N-type and impurity doping the second epitaxial layer P-type.

16. A method for manufacturing an integrated circuit comprising the steps of:

providing a silicon substrate having a first crystalline orientation;

providing a silicon layer overlying the silicon substrate, the silicon layer having a second crystalline orientation different than the first crystalline orientation;

forming a silicon on insulator layer overlying a portion of the silicon layer;

growing a first epitaxial layer having the first crystalline orientation on a portion of the silicon substrate;

growing a second epitaxial layer having the second crystalline orientation on a portion of the silicon layer; and

forming a first field effect transistor in the first epitaxial layer, a second field effect transistor in the second epitaxial layer, and a third field effect transistor in the silicon on insulator layer.

17. The method of claim 16 wherein the step of providing a silicon substrate having a first crystalline orientation comprises the step of providing a silicon substrate having a <

100>

crystalline orientation and the step of providing a silicon layer overlying the silicon substrate comprises the step of providing a silicon layer having a <

110>

orientation.

18. The method of claim 17 wherein the step of forming a first field effect transistor in the first epitaxial layer comprises the step of forming an N-channel field effect transistor and the step of forming a second field effect transistor in the second epitaxial layer comprises the step of forming a P-channel field effect transistor.

19. The method of claim 16 wherein the step of providing a silicon substrate having a first crystalline orientation comprises the step of providing a silicon substrate having a <

110>

crystalline orientation and the step of providing a silicon layer overlying the silicon substrate comprises the step of providing a silicon layer having a <

100>

orientation.

20. The method of claim 19 wherein the step of forming a first field effect transistor in the first epitaxial layer comprises the step of forming a P-channel field effect transistor and the step of forming a second field effect transistor in the second epitaxial layer comprises the step of forming an N-channel field effect transistor.

21. A method for manufacturing an integrated circuit comprising the steps of:

providing a silicon substrate having a first portion of a first crystalline orientation and a second portion of a second crystalline orientation;

forming a silicon on insulator layer overlying a portion of the silicon substrate;

growing a first epitaxial layer having the first crystalline orientation in contact with the first portion;

growing a second epitaxial layer having the second crystalline orientation in contact with the second portion;

planarizing the first epitaxial layer and the second epitaxial layer; and

forming a first field effect transistor in the first epitaxial layer, a second field effect transistor in the second epitaxial layer, and a third field effect transistor in the silicon on insulator layer.