MEMS-based, computer systems, clock generation and oscillator circuits and LC-tank apparatus for use therein

• US 6,972,635 B2
• Filed: 02/26/2003
• Issued: 12/06/2005
• Est. Priority Date: 02/26/2002
• Status: Expired due to Fees

• Current Assignee: Board of Regents of the University of Michigan (University of Michigan)
• Original Assignee: Board of Regents of the University of Michigan (University of Michigan)
• Inventors: Brown, Richard B., McCorquodale, Michael S.
• Primary Examiner(s): KINKEAD, ARNOLD M
• Application Number:
  US10/374,446
• Publication Number:
  US 20030210101A1
• Time in Patent Office: 1,014 Days
• Field of Search: 331/177.R, 331/74, 331/167, 331/117.R, 331/117.FE, 331/177.V, 331/108.C, 331/36.C, 333/262
• US Class Current: 331/167
• CPC Class Codes: H01F 17/0006 Printed inductances printed coils for dynamo-electric machines H02K3/26; printed circuits H05K
• CPC Class Codes: H01G 5/40 Structural combinations of variable capacitors with other electric elements not covered by this subclass, the structure mainly consisting of a capacitor, e.g. RC combinations
• CPC Class Codes: H01L 23/5227 Inductive arrangements or effects of, or between, wiring layers other inductive arrangements H01L23/645
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H01L 2924/3011 Impedance
• CPC Class Codes: H03B 5/1212 the amplifier comprising a pair of transistors, wherein an output terminal of each being connected to an input terminal of the other, e.g. a cross coupled pair
• CPC Class Codes: H03B 5/1228 the amplifier comprising one or more field effect transistors
• CPC Class Codes: H03B 5/124 the means comprising a voltage dependent capacitance
• CPC Class Codes: H03B 5/18 with frequency-determining element comprising distributed inductance and capacitance
• CPC Class Codes: H03B 5/32 being a piezoelectric resonator selection of piezoelectric material H10N30/00
• CPC Class Codes: H03H 2007/006 MEMS
• CPC Class Codes: H03H 7/0115 comprising only inductors and capacitors H03H7/075, H03H7/09, H03H7/12, H03H7/13 take precedence

Abstract

MEMS-based, computer system, clock generation and oscillator circuits and LC-tank apparatus for use therein are provided and which are fabricated using a CMOS-compatible process. A micromachined inductor (L) and a pair of varactors (C) are developed in metal layers on a silicon substrate to realize the high quality factor LC-tank apparatus. This micromachined LC-tank apparatus is incorporated with CMOS transistor circuitry in order to realize a digital, tunable, low phase jitter, and low power clock, or time base, for synchronous integrated circuits. The synthesized clock signal can be divided down with digital circuitry from several GHz to tens of MHz—a systemic approach that substantially improves stability as compared to the state of the art. Advanced circuit design techniques have been utilized to minimize power consumption and mitigate transistor flicker noise upconversion, thus enhancing clock stability.

Claims

1. A MEMS-based, clock generation circuit, the circuit comprising:

a substrate;

a voltage-control led oscillator fabricated on the substrate and including a MEMS LC-tank apparatus for generating a differential sinusoidal periodic signal, the LC-tank apparatus comprising a parallel plate capacitor and an inductor fabricated in a plurality of CMOS metal interconnect layers, the parallel plate capacitor comprising a top plate suspended in air over the substrate and moveable in response to a control voltage, and the inductor supported in air over the substrate; and

first circuitry also fabricated on the substrate for converting the differential sinusoidal periodic signal into a single-ended, high frequency, square-wave digital output signal.

2. The clock generation circuit as claimed in claim 1 wherein the differential sinusoidal periodic signal has an original frequency, wherein the square-wave digital output signal has a frequency of half of the original frequency, and wherein the circuit further comprises second circuitry also fabricated on the substrate for dividing the frequency of the square-wave digital output signal to at least one lower desired application frequency.

3. The clock generation circuit as claimed in claim 2 wherein the first and second circuitry and the voltage-controlled oscillator are fabricated on the substrate with a CMOS-compatible process.

4. The clock generation circuit as claimed in claim 1 wherein both the voltage-controlled oscillator and the first circuitry are fabricated on the substrate with a CMOS-compatible process.

5. The clock generation circuit as claimed in claim 4 wherein the CMOS-compatible process is a bulk or SOI CMOS process.

6. The clock generation circuit as claimed in claim 1 wherein the first circuitry also converts the differential sinusoidal periodic signal into the single-ended square-wave digital output signal at half of the original frequency.

7. The clock generation circuit as claimed in claim 2 wherein the second circuitry includes at least one flip-flop coupled to the first circuitry for dividing the frequency of the square-wave digital output signal to the at least one lower desired application frequency.

8. The clock generation circuit as claimed in claim 1 wherein the substrate is a bulk or SOI substrate.

9. A MEMS-based oscillator circuit comprising:

a substrate;

a MEMS LC-tank apparatus fabricated on the substrate with a CMOS-compatible process;

first circuitry fabricated on the substrate with the CMOS-compatible process and coupled to the LC-tank apparatus to generate a sinusoidal periodic signal having an original frequency; and

second circuitry fabricated on the substrate with the CMOS-compatible process and coupled to the first circuitry to convert the sinusoidal periodic signal to a plurality of square-wave periodic signals having a corresponding plurality of application frequencies, each application frequency of the plurality of application frequencies equal to the original frequency divided by an integer.

10. The oscillator circuit as claimed in claim 9 wherein the oscillator circuit is tunable in response to a control input to provide a variable original frequency.

11. The oscillator circuit as claimed in claim 9 wherein the CMOS-compatible process is a bulk or SOI CMOS process.

12. The oscillator circuit as claimed in claim 9 wherein the oscillator circuit is a double-balanced oscillator circuit to reduce flicker noise upconversion.

13. The oscillator circuit as claimed in claim 10 wherein the LC-tank includes at least one micromachined varactor having a capacitance which varies in response to the control input.

14. The oscillator circuit as claimed in claim 13 wherein the at least one varactor includes a top plate and wherein the circuitry includes bypass capacitors to block the control input to the top plate from the remainder of the circuitry.

15. The oscillator circuit as claimed in claim 13 wherein the oscillator circuit is a double-balanced, cross-coupled oscillator circuit to reduce flicker noise upconversion.

26. The apparatus as claimed in claim 12 wherein the top plate has a plurality of etch holes to facilitate release of the top plate during or upon completion of the CMOS-compatible process.

16. A MEMS-based, LC-tank apparatus having a high quality factor, the apparatus comprising:

a substrate;

at least one micromachined, parallel plate varactor fabricated on the substrate with a CMOS-compatible process in conductive layers;

a micromachined inductor coupled to the at least one varactor and also fabricated on the substrate with the CMOS-compatible process in a conductive layer of the conductive layers;

wherein the varactor has a first predetermined size and the inductor has a second predetermined size to generate a stable sinusoidal signal having a high original frequency during oscillation; and

circuitry coupled to the varactor and the inductor to divide the high original frequency, by a factor of two, to a lower application frequency.

17. The apparatus as claimed in claim 16 wherein the at least one varactor has a variable capacitance to provide a tuning range for the apparatus.

18. The apparatus as claimed in claim 16 wherein the inductor is suspended above the substrate and released during or upon completion of the CMOS-compatible process.

19. The apparatus as claimed in claim 16 wherein the inductor is hollow.

20. The apparatus as claimed in claim 16 wherein the inductor is suspended above the substrate by anchors that are defined by the CMOS-compatible process.

21. The apparatus as claimed in claim 17 wherein the at least one varactor has a fixed bottom plate and a movable top plate suspended above the bottom plate and released during or upon completion of the CMOS-compatible process.

22. The apparatus as claimed in claim 21 wherein the top plate deflects based on a control input to tune the capacitance of the at least one varactor.

23. The apparatus as claimed in claim 21 wherein the top plate is suspended above the bottom plate by a mechanical suspension network defined by the CMOS-compatible process.

24. The apparatus as claimed in claim 16 wherein the plurality of conductive layers are metal layers.

25. The apparatus as claimed in claim 16 wherein the CMOS-compatible process is a bulk or SOI CMOS process.

27. The apparatus as claimed in claim 16 wherein the substrate is a bulk or SOI substrate.

28. The apparatus as claimed in claim 16 wherein the original frequency during oscillation is a resonant frequency.

29. The apparatus as claimed in claim 16 wherein the at least one varactor and the inductor are defined by one or more of the following:

metal-insulator-metal (MiM) layers or metal routing layers.

30. A computer system comprising:

a databus;

a central processing unit coupled bi-directionally to the databus;

transient memory coupled bi-directionally to the databus;

persistent memory coupled bi-directionally to the databus; and

a clock generation circuit for generating a stable, square-wave digital output signal suitable for use within said computer system, the clock generation circuit comprising;

an oscillator fabricated on a substrate and including a EMS-based, LC-tank apparatus for generating a sinusoidal periodic signal having a first frequency; and

first circuitry fabricated on the substrate for converting the sinusoidal periodic signal into a plurality of high frequency square-wave digital output signals each having a second frequency, the second frequency equal to the first frequency divided by an integer.

31. A clock generation circuit, the circuit comprising:

a substrate;

a MEMS-based, LC-tank oscillator fabricated on the substrate for generating a periodic sinusoidal signal having an original frequency;

first circuitry fabricated on the substrate for converting the periodic signal into a high frequency, square-wave digital output signal having a frequency of half of the original frequency; and

second circuitry fabricated on the substrate for dividing the frequency of the square-wave digital output signal to at least one lower application frequency.

32. The clock generation circuit as claimed in claim 31 wherein the sinusoidal periodic signal is a differential signal and wherein the first circuitry converts the sinusoidal differential signal into a sinusoidal single-ended signal.

33. The clock generation circuit as claimed in claim 32 wherein the first circuitry also converts the sinusoidal single-ended signal into the square-wave digital output signal at half of the original frequency.

34. The clock generation circuit as claimed in claim 31 wherein the second circuitry includes at least one flip-flop coupled to the first circuitry for dividing the frequency of the square-wave digital output signal to the at least one lower application frequency.

35. A MEMS-based, oscillator circuit for generating a low noise, high frequency, periodic signal, the oscillator circuit comprising:

a substrate;

a high-Q MEMS LC-tank apparatus fabricated on the substrate with a CMOS-compatible process, the LC-tank comprising at least one micromachined varactor having a capacitance which varies in response to the control input and having a top plate; and

circuitry fabricated on the substrate with the CMOS-compatible process and coupled to the LC-tank apparatus to generate the periodic signal and including a bypass capacitor to block the control input to the top plate from the remainder of the circuitry.

36. A MEMS-based, LC-tank apparatus having a high quality factor, the apparatus comprising:

a substrate;

at least one micromachined varactor fabricated on the substrate with a CMOS-compatible process, the at least one micromachined varactor having a variable capacitance to provide a tuning range for the apparatus, the at least one micromachined varactor comprising a fixed bottom plate and a movable top plate suspended above the bottom plate, wherein the top plate has a plurality of etch holes to facilitate release of the top plate during or upon completion of the CMOS-compatible process; and

a micromachined inductor coupled to the at least one varactor and fabricated on the substrate with the CMOS-compatible process.

37. An integrated clock generation circuit, comprising:

a MEMS-based, LC tank oscillator circuit fabricated on a substrate for generating a first, differential periodic signal having a first frequency, the oscillator circuit comprising an inductor coupled to a capacitor; and

a frequency divider circuit fabricated on the substrate and coupled to the oscillator circuit to convert the first, differential periodic signal to a plurality of single-ended square-wave periodic application signals, each periodic application signal having a different frequency equal to an integer fraction of the first frequency.

38. The integrated clock generation circuit of claim 37, wherein a clock signal is a selected periodic application signal of the plurality of square-wave periodic application signals.

39. The integrated clock generation circuit of claim 37, wherein the oscillator circuit further comprises active devices adapted to operate at or near weak inversion.

40. The integrated clock generation circuit of claim 37, wherein the frequency divider circuit comprises:

a plurality of flip-flops coupled in succession, a clock input of a first flip-flop of the plurality coupled to the oscillator circuit to receive the first, differential periodic signal, and the output of each flip-flop providing a corresponding periodic application signal.

41. The integrated clock generation circuit of claim 37, wherein the inductor and capacitor are MEMS-based.

42. The integrated clock generation circuit of claim 37, wherein the inductor and capacitor are fabricated from one or more CMOS-compatible layers.

43. The integrated clock generation circuit of claim 42, wherein the one or more CMOS-compatible layers are one or more metal layers.

44. The integrated clock generation circuit of claim 43, wherein the inductor is supported in air over the substrate and the capacitor is suspended in air over the substrate.

45. The integrated clock generation circuit of claim 44, wherein the inductor and capacitor, following CMOS fabrication defining bond pad openings, are released in a maskless etch process.

46. The integrated clock generation circuit of claim 37, wherein the capacitor is metal-insulator-metal (MiM).

47. The integrated clock generation circuit of claim 37, wherein the capacitor is formed of CMOS-compatible metal routing layers.

48. The integrated clock generation circuit of claim 37, further comprising:

a microprocessor.

49. The integrated clock generation circuit of claim 37, further comprising:

a microcontroller.

50. The integrated clock generation circuit of claim 37, wherein phase noise decreases with each successive frequency division performed by the frequency divider.

51. The integrated clock generation circuit of claim 37, wherein periodic application signal stability improves with each successive frequency division performed by the frequency divider.

52. An integrated clock generation circuit, comprising:

an oscillator circuit fabricated on a substrate for generating a first, differential periodic signal having a first frequency, the oscillator circuit comprising an inductor coupled to a capacitor;

an amplifier fabricated on the substrate and coupled to the oscillator to convert the first, differential periodic signal to a single-ended signal having a second frequency; and

a frequency divider circuit fabricated on the substrate and coupled to the amplifier to convert the single-ended signal to a plurality of square-wave periodic application signals, each periodic application signal having a different frequency equal to the second frequency divided by an integer.

53. The integrated clock generation circuit of claim 52, wherein a clock signal is a selected periodic application signal of the plurality of square-wave periodic application signals.

54. The integrated clock generation circuit of claim 52, wherein the second frequency is equal to the first frequency.

55. The integrated clock generation circuit of claim 52, wherein the frequency divider circuit comprises:

a plurality of flip-flops coupled in succession, a clock input of a first flip-flop of the plurality coupled to the amplifier to receive the single-ended signal, and the output of each flip-flop providing a corresponding periodic application signal.

56. The integrated clock generation circuit of claim 52, wherein the inductor and capacitor are MEMS-based.

57. The integrated clock generation circuit of claim 52, wherein the inductor and capacitor are fabricated from one or more CMOS-compatible metal layers.

58. The integrated clock generation circuit of claim 57, wherein the inductor is supported in air over the substrate and the capacitor is suspended in air over the substrate.

59. The integrated clock generation circuit of claim 58, wherein the inductor and capacitor, following CMOS fabrication defining bond pad openings, are released in a maskless etch process.

60. The integrated clock generation circuit of claim 52, wherein the capacitor is metal-insulator-metal.

61. An integrated clock generation circuit, comprising:

a double-balanced LC-tank oscillator circuit fabricated from a CMOS-compatible process on a substrate, the LC-tank oscillator circuit for generating a stable differential periodic signal having a first frequency, the LC-tank oscillator circuit comprising an inductor and a capacitor fabricated from one or more CMOS-compatible layers;

an amplifier fabricated from a CMOS-compatible process on the substrate and coupled to the L-C tank oscillator circuit to convert the differential periodic signal to a single-ended signal having a second frequency; and

a frequency divider circuit fabricated on the substrate and coupled to the amplifier to convert the single-ended signal to a plurality of square-wave periodic application signals, each periodic application signal having a different frequency equal to the second frequency divided by an integer, wherein a periodic application signal of the plurality of square-wave periodic application signals is a clock signal.