Method for integrated high Q inductors in FCGBA packages

• US 6,972,965 B2
• Filed: 02/04/2003
• Issued: 12/06/2005
• Est. Priority Date: 02/04/2003
• Status: Expired due to Fees

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Sover, Ra′anan, Ravid, Shmuel
• Primary Examiner(s): Vigushin, John B.
• Application Number:
  US10/358,794
• Publication Number:
  US 20040150968A1
• Time in Patent Office: 1,036 Days
• Field of Search: 361/760, 361/777, 361/782, 361/783, 257/691, 257/700, 257/723, 257/724, 257/728, 257/778, 257/786
• US Class Current: 361/777
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/16 of an individual bump connector
• CPC Class Codes: H01L 2224/8121 using a reflow oven
• CPC Class Codes: H01L 2224/81815 Reflow soldering
• CPC Class Codes: H01L 2224/83102 using surface energy, e.g. capillary forces
• CPC Class Codes: H01L 2224/92125 the second connecting process involving a layer connector
• CPC Class Codes: H01L 23/3128 the substrate having spherical bumps for external connection
• CPC Class Codes: H01L 23/645 Inductive arrangements H01L23/647, H01L23/66 take precedence
• CPC Class Codes: H01L 24/81 using a bump connector
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/15192 Resurf arrangement of the internal vias
• CPC Class Codes: H01L 2924/15311 being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/19041 being a capacitor
• CPC Class Codes: H01L 2924/3011 Impedance

Abstract

A high quality factor on-package, off-die inductor assembly is disclosed. The assembly includes a flip-chip, ball-grid array package substrate, an on-package, off-die trace line is coupled to one or more bumps attached to an upper surface of the package substrate. The trace line has a self-inductance and a predetermined length. The quality factor associated with the inductor is a ratio of the trace line'"'"'s inductance to the trace lines resistance. The package substrate is a low loss laminate.

Claims

1. An inductor assembly, comprising:

a flip-chip, ball-grid array package substrate;

a microelectronic die coupled to one or more bumps attached to an upper surface of the package substrate; and

an on-package, off-die trace line coupled to the one or more bumps attached to the upper surface of the package substrate, wherein the trace line has an inherent self-inductance that is used in combination with on-die inductive components to achieve a predetermined frequency of resonance or other matching network of RF frequencies.

2. The inductor assembly of claim 1, wherein a length of the trace line is in the range of approximately 0.1 mm to approximately 10.0 mm.

3. The inductor assembly of claim 1, wherein no bond wires are used to couple the trace line to a microelectronic die that is attached to the package bumps.

4. The inductor assembly of claim 1, wherein no bond wires are used to couple the trace line to the package substrate or to the package bumps.

5. The inductor assembly of claim 1, wherein the trace line is not associated with interconnections on or off the package.

6. The inductor assembly of claim 2, wherein the trace line has a high quality factor, the quality factor being a ratio of the trace line'"'"'s inductance to the trace line'"'"'s resistance.

7. The inductor assembly of claim 6, further comprising:

a molded encapsulation material attached to the upper surface of the package substrate and covering the microelectronic die to form a protective housing.

8. The inductor assembly of claim 7, wherein EMI/RFI emissions associated with the trace line are substantially contained within the package and do not substantially interfere with other board signals.

9. The inductor assembly of claim 6, wherein the trace line is a component of a low phase noise voltage controlled oscillator or other matching network for RF frequencies.

10. The inductor assembly of claim 1, further comprising:

a wireless transceiver coupled to a low phase voltage controlled oscillator or other matching networks of RF frequencies.

11. The inductor assembly of claim 10, wherein the frequency of resonance is in the range of approximately 0.1 Ghz to approximately 100 GHz.

12. The inductor assembly of claim 10, wherein the trace line'"'"'s self-inductance contributes to a reduced bit error rate in the wireless transceivers.

13. The inductor assembly of claim 10, wherein the frequency of resonance is in the range of approximately 0.1 Ghz to approximately 100 GHz.

14. A wireless communications device, comprising:

a package substrate;

a plurality of bumps disposed on an upper surface of the package substrate;

a microelectronic die coupled to the plurality of bumps; and

an on-laminate, off-die trace line having an inherent self-inductance;

the trace line coupled to one or more of the plurality of bumps, the trace line'"'"'s self-inductance used in combination with on-die inductive components to achieve a predetermined frequency of response.

15. The wireless communications device of claim 14, further comprising:

a low phase noise voltage controlled oscillator formed on the package substrate; and

a wireless transceiver coupled with the low phase noise voltage controlled oscillator or other matching networks of RF frequencies.

16. The wireless communications device of claim 15, wherein the trace line is a component of the low phase voltage noise controlled oscillator or other matching networks of RF frequencies.

17. The wireless communications device of claim 16, wherein no bond wires are used to couple the trace line to the microelectronic die.

18. The wireless communications device of claim 16, wherein the trace line'"'"'s self-inductance contributes to a reduced bit error rate in the wireless transceiver.

19. The wireless communications device of claim 16, wherein the predetermined frequency of response is in a range of approximately 0.1 GHz to 100 Ghz.

20. The wireless communications device of claim 15, wherein the trace line has a high quality factor, the quality factor being a ratio of the trace line'"'"'s inductance to the trace line'"'"'s resistance.

21. A computer comprising:

a bus;

a processor coupled to the bus;

memory device coupled to the bus to store computer readable instructions to be executed by the processor;

a wireless transceiver coupled to the bus to transmit and receive data over a predetermined radio frequency; and

a semiconductor package associated with the bus, the package including;

a package substrate;

a microelectronic die connected to the substrate; and

an on-substrate, off-die trace line formed on the upper surface of the package substrate, the trace line having an inherent self-inductance being coupled to one or more of a plurality of bumps attached to the upper surface of the substrate, the self-inductance used in combination with on-die inductive components to achieve a predetermined frequency of resonance or other matching network of RF frequencies.

22. The computer of claim 21, further comprising:

a low phase noise voltage controlled oscillator formed on the package substrate, wherein the trace line is a component of a low phase noise voltage controlled oscillator.

23. The computer of claim 22, wherein the trace line has a high quality factor, the quality factor being a ration of the trace line'"'"'s inductance to the trace line'"'"'s resistance.

24. The computer of claim 22, wherein no bond wires are used to couple the trace line to the package substrate.

25. The computer of claim 22, wherein the radio frequency is in the range of approximately 0.1 GHz to approximately 100 GHz.

26. The computer of claim 21, further comprising:

a wireless transceiver formed on the package substrate, wherein the trace line is a component of impedance matching of RF networks.