Switching fabric for interfacing a host processor and a plurality of network modules

• US 6,973,093 B1
• Filed: 12/29/2000
• Issued: 12/06/2005
• Est. Priority Date: 12/29/2000
• Status: Active Grant

• Current Assignee: Cisco Technology, Inc. (Cisco Systems, Inc.)
• Original Assignee: Cisco Technology, Inc. (Cisco Systems, Inc.)
• Inventors: Shroff, Chirag, Briddell, Dennis M.
• Primary Examiner(s): Pham, Chi
• Assistant Examiner(s): JONES, PRENELL P
• Application Number:
  US09/751,719
• Time in Patent Office: 1,803 Days
• Field of Search: 370/421, 370/427, 352/223, 218/258, 219384- 395, 360/489, 360/216, 360427-429, 729/212, 729/218, 729/219, 729/220, 729/224, 710/5, 710306-310, 710/300, 710/315, 710/110, 710/108, 710/152, 710/311, 710/314, 710/100, 710/260, 710/219, 710/312, 379 9001- 9307, 709/213, 709/216, 709/203, 348/143
• US Class Current: 370/421
• CPC Class Codes: H04L 49/102 using shared medium, e.g. bus or ring
• CPC Class Codes: H04L 49/254 Centralised controller, i.e. arbitration or scheduling
• CPC Class Codes: H04L 49/602 Multilayer or multiprotocol switching, e.g. IP switching

Abstract

An information transport system includes a switching fabric that transfers information between network modules and between a host processor and the network modules. The switching fabric includes network module interfaces each associated with one or more network modules. The network module interfaces communicate with each other over a peer transaction bus to allow information to be transferred from one network module to another network module. The switching fabric also includes a processor interface associated with the host processor. The processor interface communicates with the network module interfaces over a host transaction bus to allow information transfer between the host processor and each network module. The peer transaction bus and the host transaction bus separately support routed packet data and peer to peer data transactions in order to prevent one type of transaction from blocking the other and avoid performance dependencies.

Claims

1. A switching fabric for interfacing a host processor and a plurality of network modules, comprising:

a plurality of network module interfaces, each network module interface operable to communicate with one or more associated network modules over a module communication link, the plurality of network modules operable to communicate among one another over a peer transaction bus interconnecting the plurality of network module interfaces;

a processor interface operable to communicate with a host processor over a host communication link, the processor interface operable to communicate with the plurality of network module interfaces over a host transaction bus, the peer transaction bus being separate from the host transaction bus to prevent transactions from blocking other transactions on either of the peer transaction bus and the host transaction bus and avoid performance dependencies therein.

2. The switching fabric of claim 1, wherein the module communication link which each of the plurality of network module interfaces communicates with its associated network modules is a Peripheral Component Interconnect (PCI) bus.

3. The switching fabric of claim 2, wherein each of the plurality of network module interfaces is operable to convert between a protocol of the PCI bus and protocols of the peer transaction bus and the host transaction bus.

4. The switching fabric of claim 1, wherein the host communication link which the processor interface communicates with the host processor is a Peripheral Component Interconnect (PCI) bus.

5. The switching fabric of claim 4, wherein the processor interface is operable to convert between a protocol of the PCI bus and a protocol of the host transaction bus.

6. The switching fabric of claim 1, further comprising:

a peer transaction bus controller operable to control information transfer across the peer transaction bus;

a host transaction bus controller operable to control information transfer across the host transaction bus.

10. The switching fabric of claim 1, wherein the host communication link and the module communication links operate at different clock frequencies.

7. A switching fabric for interfacing a host processor and a plurality of network modules, comprising:

a plurality of network module interfaces, each network module interface operable to communicate with one or more associated network modules over a module communication link, the plurality of network modules operable to communicate among one another over a peer transaction bus;

a processor interface operable to communicate with a host processor over a host communication link, the processor interface operable to communicate with the plurality of network module interfaces over a host transaction bus;

wherein each of the plurality of network module interfaces includes;

a network module interface core operable to convert between a protocol of the module communication link between each of the plurality of network module interfaces and their respective network modules and protocols of the peer transaction bus and the host transaction bus;

a peer ingress buffer operable to receive information from an associated network module for transfer onto the peer transaction bus;

a peer egress buffer operable to receive information from a remote network module over the peer transaction bus for transfer to an appropriate associated network module;

a network module write posting buffer operable to receive communications from an associated network module destined for the host processor for transfer onto the host transaction bus;

a network module delayed read buffer operable to receive information from the host processor over the host transaction bus for transfer to an appropriate associated network module.

8. A switching fabric for interfacing a host processor and a plurality of network modules, comprising:

a plurality of network module interfaces, each network module interface operable to communicate with one or more associated network modules over a module communication link, the plurality of network modules operable to communicate among one another over a peer transaction bus;

a processor interface operable to communicate with a host processor over a host communication link, the processor interface operable to communicate with the plurality of network module interfaces over a host transaction bus;

wherein the processor interface includes;

a processor interface core operable to convert between a protocol of the host communication link between the host processor and the processor interface and a protocol of the host transaction bus;

a host delayed read buffer operable to receive information from the host processor for transfer to a network module over the host transaction bus;

a processor initiator write buffer operable to receive information over the host transaction bus from a network module for transfer to the host processor.

9. A switching fabric for interfacing a host processor and a plurality of network modules, comprising:

a plurality of network module interfaces, each network module interface operable to communicate with one or more associated network modules over a module communication link, the plurality of network modules operable to communicate among one another over a peer transaction bus;

a processor interface operable to communicate with a host processor over a host communication link, the processor interface operable to communicate with the plurality of network module interfaces over a host transaction bus;

wherein a clock driving the host transaction bus and the peer transaction bus is derived from a clock driving the host communication link.

11. A switching fabric for interfacing a host processor and a plurality of network modules, comprising:

a plurality of network module interfaces, each network module interface operable to communicate with one or more associated network modules over a module communication link, the plurality of network modules operable to communicate among one another over a peer transaction bus;

a processor interface operable to communicate with a host processor over a host communication link, the processor interface operable to communicate with the plurality of network module interfaces over a host transaction bus;

wherein the peer transaction bus carries layer two traffic and the host transaction bus carries layer three traffic.

12. The switching fabric of claim 11, wherein the layer two traffic is in asynchronous transfer mode cells.

13. A method for interfacing a host processor and a plurality of network modules, comprising:

providing a module communication link between a network module interface and associated network modules;

providing a peer transaction path between a plurality of the network module interfaces to allow communications between non-associated network modules;

providing a host communication link between a processor interface and a host processor;

providing a host transaction path between the processor interface and the plurality of network module interfaces to allow communications between the host processor and all network modules, the peer transaction path being separate from the host transaction path to prevent transactions from blocking other transactions on either of the peer transaction bus and the host transaction bus and avoid performance dependencies therein.

14. The method of claim 13, further comprising:

sending information between the host processor and the processor interface using a Peripheral Component Interface (PCI) bus protocol.

15. The method of claim 14, further comprising:

converting the PCI bus protocol to and from a protocol of the host transaction path.

16. The method of claim 15, further comprising:

converting the protocol of the host transaction path to and from a protocol of the module communication link.

17. The method of claim 16, wherein the protocol of the module communication link is the PCI bus protocol.

18. The method of claim 13, further comprising:

sending information between a network module and its associated network module interface using a Peripheral Component Interface (PCI) bus protocol.

19. The method of claim 18, further comprising:

converting the PCI bus protocol to and from a protocol of the peer transaction path.

20. A switching fabric for interfacing a host processor and a plurality of network modules, comprising:

means for providing communications with one or more associated network modules over a module communication link;

means for providing communications among non-associated network modules;

means for providing communications with a host processor over a host communication link;

means for providing communications between the host processor and all network modules, wherein non-associated network module communications are maintained separately from host processor to and from network module communications to prevent transactions from blocking other transactions associated with either the non-associated network module communications and the host processor to and from network module communications and avoid performance dependencies therein.