Linearizer for a PIN diode attenuator
First Claim
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1. A system for providing linearized operation of a RF circuit, said system comprising:
- a first transistor differential pair;
a second transistor differential pair;
a control signal input port;
a first control signal output port, wherein said first control signal output port is coupled to said control signal input port through said first transistor differential pair;
a second attenuator control signal output port, wherein said second control signal output port is coupled to said control signal input port through said second transistor differential pair; and
a temperature compensation circuit coupled to said control signal input port to provide temperature compensation with respect to a control signal applied thereto.
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Abstract
Linearizer circuitry is disclosed for providing control signal outputs to operate a controllable attenuator throughout a relatively large dynamic range while maintaining a relatively consistent return loss. Preferred embodiment linearizer circuitry provides a series control current and a shunt control current for coupling to a PIN diode attenuator, such as may be configured in a π network or a T network. Preferably, differential pairs are utilized in providing each of the control current outputs.
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Citations
33 Claims
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1. A system for providing linearized operation of a RF circuit, said system comprising:
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a first transistor differential pair; a second transistor differential pair; a control signal input port; a first control signal output port, wherein said first control signal output port is coupled to said control signal input port through said first transistor differential pair; a second attenuator control signal output port, wherein said second control signal output port is coupled to said control signal input port through said second transistor differential pair; and a temperature compensation circuit coupled to said control signal input port to provide temperature compensation with respect to a control signal applied thereto. - View Dependent Claims (2, 3, 4, 5, 6, 12, 13, 21, 22)
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7. A system for providing linearized operation of a RF circuit, said system comprising:
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a first transistor differential pair; a second transistor differential pair; a control signal input port, wherein said control signal input port is coupled to said first transistor differential pair at a base of one transistor of said first transistor differential pair, wherein a base of another transistor of said first transistor differential pair is coupled substantially directly to a ground point; a first control signal output port, wherein said first control signal output port is coupled to said control signal input port through said first transistor differential pair; and a second attenuator control signal output port, wherein said second control signal output port is coupled to said control signal input port through said second transistor differential pair.
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8. A system for providing linearized operation of a RF circuit, said system comprising:
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a first transistor differential pair; a second transistor differential pair; a control signal input port, wherein said control signal input port is coupled to said first transistor differential pair at a base of one transistor of said first transistor differential pair; a first control signal output port, wherein said first control signal output port is coupled to said control signal input port through said first transistor differential pair; a second attenuator control signal output port, wherein said second control signal output port is coupled to said control signal input port through said second transistor differential pair; and a first current source circuit, wherein said first current source circuit is coupled to a collector of said same transistor of said first second transistor differential pair that said control signal input port is coupled to said base of. - View Dependent Claims (9, 10, 11)
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14. A system for providing linearized operation of a RF circuit, said system comprising:
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a first transistor differential pair; a second transistor differential pair; a control signal input port, wherein said control signal input port is coupled to said second transistor differential pair at a base of one transistor of second transistor differential pair, wherein a base of another transistor of said second transistor differential pair is coupled to a ground point; a first control signal output port, wherein said first control signal output port is coupled to said control signal input port through said first transistor differential pair; and a second attenuator control signal output port, wherein said second control signal output port is coupled to said control signal input port through said second transistor differential pair.
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15. A system for providing linearized operation of a RF circuit, said system comprising:
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a first transistor differential pair; a second transistor differential pair; a control signal input port, wherein said control signal input port is coupled to said second transistor differential pair at a base of one transistor of second transistor differential pair; a first control signal output port, wherein said first control signal output port is coupled to said control signal input port through said first transistor differential pair; a second attenuator control signal output port, wherein said second control signal output port is coupled to said control signal input port through said second transistor differential pair; and a second current source circuit, wherein said second current source circuit is coupled to an emitter of two transistors of said second transistor differential pair including said same transistor of said second transistor differential pair that said control signal input port is coupled to said base of. - View Dependent Claims (16, 17, 18)
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19. A system for providing linearized operation of a RF circuit, said system comprising:
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a first transistor differential pair; a second transistor differential pair; a control signal input port; a first control signal output port, wherein said first control signal output port is coupled to said control signal input port through said first transistor differential pair; and a second attenuator control signal output port, wherein said second control signal output port is coupled to said control signal input port through said second transistor differential pair, wherein a second control signal output at said second control signal output port is directly related to a difference of a collector current of a transistor of said second transistor differential pair and a collector current of another transistor of said second transistor differential pair.
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20. A system for providing linearized operation of a RF circuit, said system comprising:
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a first transistor differential pair; a second transistor differential pair; a control signal input port; a first control signal output port, wherein said first control signal output port is coupled to said control signal input port through said first transistor differential pair; a second attenuator control signal output port, wherein said second control signal output port is coupled to said control signal input port through said second transistor differential pair; and a first current mirror coupled to said first transistor differential pair, wherein said first control signal output port is coupled to said first transistor differential pair through said first current mirror.
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23. A system for providing linearized operation of a RF circuit, said system comprising:
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a first transistor differential pair; a second transistor differential pair; a control signal input port; a first control signal output port, wherein said first control signal output port is coupled to said control signal input port through said first transistor differential pair; a second attenuator control signal output port, wherein said second control signal output port is coupled to said control signal input port through said second transistor differential pair; and a second current mirror coupled to said second transistor differential pair, wherein said second control signal output port is coupled to said second transistor differential pair through said second current mirror.
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24. A system for providing linearized operation of a PIN diode attenuator, said system comprising:
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a first transistor differential pair; a second transistor differential pair; a control signal input port, wherein said control signal input port accepts an attenuator control voltage applied thereto, wherein said control signal input port is coupled to said first and second transistor differential pairs at a base of one transistor of each of said first and second transistor differential pairs, and wherein a base of another transistor of each of said first and second transistor differential pairs is coupled substantially directly to a ground point; a first control signal output port, wherein said first control signal output port is coupled to said control signal input port through said first transistor differential pair, wherein a first control signal output at said first control signal output port is a series PIN diode bias current; and a second attenuator control signal output port, wherein said second control signal output port is coupled to said control signal input port through said second transistor differential pair, wherein a second control signal output at said second control signal output port is a shunt PIN diode bias current. - View Dependent Claims (25)
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26. A system for providing linearized operation of a PIN diode attenuator, said system comprising:
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a first transistor differential pair; a second transistor differential pair; a control signal input port, wherein said control signal input port accepts an attenuator control voltage applied thereto, and wherein said control signal input port is coupled to said first and second transistor differential pairs at a base of on transistor of each of said first and second transistor differential pairs; a first control signal output port, wherein said first control signal output port is coupled to said control signal input port through said first transistor differential pair, wherein a first control signal output at said first control signal output port is a series PIN diode bias current, wherein said first control signal output at said first control signal output port is directly related to a collector current of another transistor of said first transistor differential pair; a second attenuator control signal output port, wherein said second control signal output port is coupled to said control signal input port through said second transistor differential pair, wherein a second control signal output at said second control signal output port is a shunt PIN diode bias current, wherein said second control signal output at said second control signal output port is directly related to a difference of a collector current of a transistor of said second transistor differential pair and a collector current of another transistor of said second transistor differential pair; and a first current source circuit, wherein said first current source circuit is coupled to a collector of said same transistor of said first second transistor differential pair that said control signal input port is coupled to said base of; and a second current source circuit, wherein said second current source circuit is coupled to an emitter of two transistors of said second transistor differential pair including said same transistor of said second transistor differential pair that said control signal input port is coupled to said base of. - View Dependent Claims (27, 28, 29)
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30. A method for providing linear operation of an attenuator, said method comprising:
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accepting a control signal at a linearizer input port, wherein a signal accepted at said linearizer input port is a control voltage coupled to a base of a transistor of a first transistor differential pair and a base of a transistor of a second transistor pair; outputting a first control signal at a first linearizer output port, wherein said first control signal is a first bias current corresponding to a collector current of said first transistor differential pair; outputting a second control signal at a first linearizer output port, wherein said second control signal is a second bias current corresponding to a difference between collector currents of said second transistor differential pair; and compensating said control voltage accepted at said linearizer input port for temperature. - View Dependent Claims (31)
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32. A method for providing linear operation of an attenuator, said method comprising:
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accepting a control signal at a linearizer input port, wherein a signal accepted at said linearizer input port is a control voltage coupled to a base of a transistor of a first transistor differential pair and a base of a transistor of a second transistor pair; outputting a first control signal at a first linearizer output port, wherein said first control signal is a first bias current corresponding to a collector current of said first transistor differential pair, wherein another collector current of said first transistor differential pair is controlled to substantially correspond to the value (8 K)/Z0, wherein K is a constant of a component of said attenuator and Z0 is the characteristic impedance of a system into which said attenuator is inserted; and outputting a second control signal at a first linearizer output port, wherein said second control signal is a second bias current corresponding to a difference between collector currents of said second transistor differential pair.
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33. A method for providing linear operation of an attenuator, said method comprising:
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accepting a control signal at a linearizer input port, wherein a signal accepted at said linearizer input port is a control voltage coupled to a base of a transistor of a first transistor differential pair and a base of a transistor of a second transistor pair; outputting a first control signal at a first linearizer output port, wherein said first control signal is a first bias current corresponding to a collector current of said first transistor differential pair; and outputting a second control signal at a first linearizer output port, wherein said second control signal is a second bias current corresponding to a difference between collector currents of said second transistor differential pair, wherein a sum of emitter currents of said second transistor differential pair is controlled to substantially correspond to the value (2 K)/ (Z0−
RS), wherein K and RS are constants of a component of said attenuator and Z0 is the characteristic impedance of a system into which said attenuator is inserted.
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Specification