Partition formation using microprocessors in a multiprocessor computer system

• US 6,973,517 B1
• Filed: 08/31/2000
• Issued: 12/06/2005
• Est. Priority Date: 08/31/2000
• Status: Expired due to Term

• Current Assignee: Hewlett Packard Enterprise Development LP (Hewlett-Packard Enterprise Company)
• Original Assignee: Hewlett-Packard Development Company, L.P. (HP Inc.)
• Inventors: Bracken, Richard Edward, Golden, David, Mazur, Dennis
• Primary Examiner(s): Follansbee, John
• Assistant Examiner(s): Nguyen, Dustin
• Application Number:
  US09/652,458
• Time in Patent Office: 1,923 Days
• Field of Search: 712/13, 712/20, 712/23, 712/203
• US Class Current: 710/104
• CPC Class Codes: G06F 15/16 Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs coordinating program control therefor G06F9/52; in regulating and control system G05B

Abstract

The invention is a control system using microprocessors which communicate through a Local Area Network (private LAN) to control operation of both processors and input and output subsystems (IO system) of a multiprocessor computer system. The processors each have memory associated therewith, and each processor has an IO system comprising a plurality of busses such as PCI busses, associated therewith. The processors are cabled together in a mesh arrangement so that messages can be transferred between any of the processors and delivered to memory associated with the destination processor, or delivered to an IO system associated with the destination processor, etc. The microprocessors are powered on when power is applied to the chassis of the multiprocessor system, and the microprocessors then control the processors of the multiprocessor system, including applying power to the processors, forming hard partitions containing selected processors, computing routes from a processor to a memory associated with any processor for read and write transactions, computing routes to IO subsystems associated with any processor of the hard partition, forming partition boundaries so that processors in one hard partition cannot read and write to memory or IO systems associated with processors in another hard partition, forming soft partitions of processors, controlling boot-up of operating systems executing on the processors of the multiprocessor computer system, removing power from a failed processor, providing power to a repaired processor, etc.

Claims

1. A multiprocessor computer system having a plurality of processors interconnected so that they can share memory, comprising:

a plurality of links, each link of said plurality of links connecting a processor to another processor;

a router box (RBOX) associated with each processor of said plurality of processors, said RBOX arranged to forward a message received on an input link of said plurality of links from a source processor to an outgoing link of said plurality of links toward a destination processor in response to data carried in said message;

a plurality of microprocessors, each of said microprocessors having a microprocessor memory associated therewith, a selected microprocessor of said plurality of microprocessor associated with at least one processor of said plurality of processors, said plurality of microprocessors arranged to control said plurality of processors, said control including applying electric power to a selected processor and removing electric power from said selected processor;

a data structure stored in microprocessor memory, said data structure storing a representation of the links connecting said processors and storing routes used by said RBOX in routing messages along said links, a copy of said data structure stored in microprocessor memory of each of said microprocessors; and

,

a process to update said data structure in each said microprocessor memory in the event that a change occurs in a status of a component of said multiprocessor computer system.

2. The multiprocessor computer system of claim 1 further comprising:

a process executing in said microprocessors for directing said microprocessors in formation of a partition of said processors, said partition having a selected number of said processors as members, said members capable of reading and writing a common memory within said partition, and other non-member processors excluded from reading and writing said common memory; and

,

a second data structure for storing a representation of said partitions, and storing routes through said links for transfer of messages between processors within a partition but not between processors of different partitions.

3. The multiprocessor computer system of claim 2 wherein the microprocessors are interconnected through a local area network, the system further comprising:

a management computer communicating through said local area network with said microprocessors, said management computer having an input device for entering commands to said plurality of microprocessors to modify said second data structure in order to establish the processors belonging to a partition, said multiprocessor computer system supporting a plurality of said partitions; and

a process responsive to said second data structure, said process executing in said microprocessors to establish that a processor in a partition can read and write memory associated with other processors of said partition, but cannot read and write memory associated with processors which are not members of said partition.

4. The multiprocessor computer system of claim 1 wherein the microprocessors are interconnected through a local area network, the system further comprising:

an input/output (IO) subsystem associated with at least one processor of said plurality of processors;

an IO microprocessor associated with each said IO subsystem, said IO microprocessor communicating with said microprocessors through said local area network, each said IO microprocessor having an IO microprocessor memory holding a copy of said second data structure;

a process executing in said IO microprocessor, said process responsive to said second data structure said process to apply power or remove power to said IO subsystem.

5. The multiprocessor computer system of claim 1 further comprising:

a boot-up process executing in microprocessors of said plurality of microprocessors, said boot-up process to start execution of said processors of said multiprocessor system, and said multiprocessor system capable of continuing operation, after start of execution of said processors, to permit removal of a microprocessor from the multiprocessor system without interrupting execution of said processors.

6. A method for operating a multiprocessor computer system, comprising:

connecting a plurality of processors so that they can share memory, a processor of said plurality of processors connected to another processor by at least one link of a plurality of links;

associating a router box (RBOX) with each processor of said plurality of processors, said RBOX arranged to forward a message received on an input link of said plurality of links from a source processor to an outgoing link of said plurality of links toward a destination processor in response to data carried in said message;

interconnecting a plurality of microprocessors, each of said microprocessors having a microprocessor memory associated therewith, a selected microprocessor of said plurality of microprocessors associated with at least one processor of said plurality of processors, said plurality of microprocessors arranged to control said plurality of processors, said control including applying electric power to a selected processor and removing electric power from said selected processor;

storing a data structure in microprocessor memory, said data structure storing a representation of the links connecting said processors and storing routes used by said RBOX in routing messages along said links, a copy of said data structure stored in microprocessor memory of each of said microprocessors; and

,

updating said data structure in each said microprocessor memory in the event that a change occurs in a status of a component of said multiprocessor computer system.

7. The method of claim 6, further comprising:

executing a process in said microprocessors for directing said microprocessors in formation of a partition of said processors, said partition having a selected number of said processors as members, said members capable of reading and writing a common memory within said partition, and other non-member processors excluded from reading and writing said common memory; and

,

storing in a second data structure a representation of said partitions, and storing routes in said second data structure through said links, said routes for transfer of messages between processors within a partition but not between processors of different partitions.

8. The method of claim 6, further comprising:

establishing communication between a management computer and said microprocessors through said local area network, said management computer having an input device for entering commands to said plurality of microprocessors to modify said second data structure in order to establish the processors belonging to a partition, said multiprocessor computer system supporting a plurality of said partitions;

establishing, in response to said second data structure, that a processor in a partition can read and write memory associated with other processors of said partition, but cannot read and write memory associated with processors which are not members of said partition.

9. The method of claim 6, further comprising:

associating an input/output (IO) subsystem with selected processors of said plurality of processors;

associating an IO microprocessor with each said IO subsystem, said IO microprocessor communicating with said microprocessors through said local area network, each said IO microprocessor having an IO microprocessor memory holding a copy of said second data structure;

executing a process in said IO microprocessor, said process responsive to said second data structure, said process to apply power or remove power to said IO subsystem.

10. The method as in claim 6, further comprising:

executing a boot-up process in microprocessors of said plurality of microprocessors, said boot-up process to start execution of said processors of said multiprocessor system, and said multiprocessor system capable of continuing operation, after start of execution of said processors, to permit removal of a microprocessor from the multiprocessor system without interrupting execution of said processors.