Data storage system having atomic memory operation

• US 6,973,551 B1
• Filed: 12/30/2002
• Issued: 12/06/2005
• Est. Priority Date: 12/30/2002
• Status: Active Grant

• Current Assignee: Emc IP Holding Company LLC (Dell Technologies Inc.)
• Original Assignee: EMC Corporation (Dell Technologies Inc.)
• Inventors: Walton, John K.
• Primary Examiner(s): Sparks, Donald
• Assistant Examiner(s): FARROKH, HASHEM
• Application Number:
  US10/331,366
• Time in Patent Office: 1,072 Days
• Field of Search: 711/155, 711/220, 712221-224
• US Class Current: 711/155
• CPC Class Codes: G06F 9/30014 with variable precision
• CPC Class Codes: G06F 9/3004 to perform operations on memory

Abstract

A method and system for enabling a director to perform an atomic read-modify-write operation on plural bit read data stored in a selected one of a plurality of memory locations. The method includes providing a plurality of successive full adders, each one of the full adders being associated with a corresponding one of the bits of the plural bit read data. Each one of the full adders has a summation output, a carry bit input and a carry bit output. The method includes adding in each one of the full adders: (a) a corresponding bit of plural bit input data provided by the director; (b) the corresponding one of the bits of the plural bit read data; and, (c) a carry bit fed the carry bit input from a preceding full adder. Each one of the full adders provides: (a) a carry bit on the carry output thereof representative of the most significant bit produced by the full adder; and, (b) a bit on the summation output representative of a least significant bit produced by the full adder. The bit on the summation output is stored in a corresponding bit location in the selected one of a plurality of memory locations. The method selectively couples, or inhibits coupling, the carry bit produced from one of the full adders to the carry bit input of a next successive full adder selectively in accordance with a corresponding bit of a plural bit carry bit mask provided by the director providing a full adder for each one of the bits of the plural bit read stored. The full adder has a carry bit input and a carry bit output. The method includes adding each one of a bits of plural bit input data provided by the director with a corresponding one of the bits of the plural bit read data in the provided full adder together with a carry bit fed the carry bit input of such provided full adder. The full adder provides: a carry output bit; and, a summation of the bits fed to such provided full adder to the corresponding bit location in the selected one of a plurality of memory locations. The method selectively couples, or inhibits coupling, a carry bit produced by one full adder provided for a lower order bit of the plural bit read data to the carry bit input of a second full adder provided by for next, successive higher order bit of the plural bit read data selectively in accordance with one of a plurality of bits of a carry bit mask provided by the director.

Claims

1. A method for a director to perform an atomic read-modify-write operation on plural bit read data stored in a selected one of a plurality of memory locations, comprising:

providing a plurality of successive full adders, each one of the full adders being associated with a corresponding one of the bits of the plural bit read data, each one of the full adders having;

a summation output;

a carry bit input; and

a carry bit output;

summing in each one of the full adders;

(a) a corresponding bit of plural bit input data provided by the director;

(b) the corresponding one of the bits of the plural bit read data; and

, (c) a carry bit fed the carry bit input from a preceding full adder, each one of the full adders producing;

(a) a carry bit on the carry output thereof representative of the most significant bit produced by the full adder; and

, (b) a bit on the summation output representative of a least significant bit produced by the full adder;

storing the summation output in a corresponding bit location in the selected one of a plurality of memory locations; and

selectively coupling, or inhibited from coupling, the carry bit produced by one of the full adders to the carry bit input of a next successive full adder selectively in accordance with a corresponding bit of a plural bit carry bit mask provided by the director.

2. A method for selectively modifying at least one bit of plural bit data read from a memory, comprising:

reading the plural bit data from the memory from a selected one of a plurality of memory addresses;

feeding each one of the bits of the plural bit input data and each one of the bits of the plural bit data read from the memory from the selected one of a plurality of memory addresses to a corresponding one of a plurality of successively coupled full adder sections, each one of adder sections having a carry bit input, a carry bit output; and

a summation output;

coupling, or inhibiting from such coupling, the carry bit output produced by each one of the carry bit input of the succeeding one of the full adder sections selectively in accordance with a corresponding one of the bits of the plural bit mask data;

coupling the summation output of each one of the full adder sections to a corresponding one of a plurality of bit storage locations in the memory, the plurality of bit storage locations having the selected one of the plurality of memory addresses.

3. A system, comprising:

(A) a memory printed circuit board, such printed circuit board having a memory;

(B) a plurality of directors, each one being coupled to the memory board by a bus, such directors providing control and address signals to the memory to read data stored in such memory and to write data into such memory;

(C) a logic section disposed on the memory printed circuit board, such logic section being coupled between the memory and the plurality of directors, such logic section comprising;

(a) a write buffer for receiving the write data from the plurality of directors;

(b) a read buffer for receiving read data from the memory at an address provided by the address signal, such read buffer providing such read data from the memory to the plurality of directors and to the write buffer; and

(c) a read-modify-write unit fed by;

the write data and the read data from the memory and received by the read buffer, such read-modify-write unit processing the write data and the read data in the read buffer and the write buffer and for feeding such processed data for storage in such memory at an address provided by the address signal.

4. A read-modify-write system, comprising:

(a) a memory;

(b) a write buffer for receiving data, such data comprising;

plural bit write data; and

plural bit carry bit mask data;

(c) a read buffer for receiving plural bit data read from the memory, such read buffer providing such plural bit data read from the memory at an address;

(d) an arithmetic unit fed by;

the plural bit write data and the plural bit carry bit mask received in the write buffer; and

, the plural bit data read from the memory and received by the read buffer, such arithmetic unit comprising;

(i) a plurality of successively arranged full adder sections, each one of such full adder sections having;

a pair of data bit inputs; and

a carry bit input; and

wherein the pair of data bit inputs are coupled to a corresponding one of the plural bits of the write data and a corresponding one of the plural bits of the data received by the read buffer;

each one of the full adder sections producing;

a summation bit; and

,

a carry bit, such summation bit being fed to the memory for storage in such memory at the address; and

(ii) a plurality of gates, each one of the gates having one input fed by the carry bit produced by a preceding one of the successively arranged adder sections and another input fed by a corresponding one of bits of a carry bit mask, each one of such gates having an output coupled to the carry bit input of a succeeding one of the successively arranged adder section each one of such gates passing, or inhibiting from passing, the carry bit fed thereto to the output thereof selectively in accordance with the carry bit coupled to the carry bit input thereof.

5. A read-modify-write system, comprising:

(A) a memory;

(B) a director coupled to the memory for providing control signals to the memory to read data stored in such memory and to write data to be stored in such memory at an address provided by an address signal;

(C) a read-modify-write unit coupled between the memory and the director, comprising;

(a) a write buffer for receiving the data from the director, such data comprising;

plural bit write data; and

plural bit carry bit mask data;

(b) a read buffer for receiving plural bit data read from the memory at the address provided by the address signal, such read buffer providing such plural bit data read from the memory to the director and to the write buffer;

(c) an arithmetic unit fed by;

the plural bit data and the plural bit carry bit mask data received in the write buffer; and

, the plural bit data read from the memory and received by the read buffer, such arithmetic unit comprising a full adder, such full adder comprising a plurality of successively arranged full adder sections, each one of such full adder sections having a pair of data bit inputs and a carry bit input, the pair of data bit inputs being coupled to a corresponding one of the plural bits of the write data and a corresponding one of the plural bits of the data received by the read buffer, each one of the adder sections producing;

a summation bit; and

, a carry bit, such summation bit being fed to the memory for storage in such memory at the address provided by the address signal; and

(d) wherein the arithmetic section includes a plurality of gates, each one of the gates having one input fed by the carry bit produced by a preceding one of the successively arranged adder sections and another input fed by a corresponding one of the bits of a carry bit mask, each one of such gates having an output coupled to the carry bit input of a succeeding one of the successively arranged adder section each one of such gates passing, or inhibiting from passing, the carry bit fed thereto to the output thereof selectively in accordance with the carry bit coupled to the carry bit input thereof.

6. A system, comprising:

(A) a memory;

(B) a plurality of directors, each one being coupled to the memory for providing control and address signals to the memory to read data stored in such memory and to write data into such memory;

(C) a logic section coupled between the memory and the plurality of directors, such logic section comprising;

(i) a data logic section for processing data passing between the memory and the plurality of directors;

(ii) a control section coupled to the plurality of directors for providing the address and control signals to the memory in response to address and control signals fed thereto by the plurality of directors;

(iii) wherein such data logic section comprises;

(a) a write buffer for receiving data from the plurality of directors, such data comprising;

plural bit write data and plural bit carry bit mask;

(b) a read buffer for receiving plural bit data read from the memory at an address provided by the address signal, such read buffer providing such data read from the memory to the plurality of directors and to the write buffer;

(c) an arithmetic unit fed by;

the plural bit write data and the plural bit carry bit mask received in the write buffer; and

, the plural bit data read from the memory and received by the read buffer, such arithmetic unit comprising a plurality of successively arranged full adder sections, each one of such full adder sections having a pair of data bit inputs and a carry bit input, the pair of data bit inputs being coupled to a corresponding one of the plural bits of the write data and a corresponding one of the plural bits of the data received by the read buffer, each one of the adder sections producing;

a summation bit and a carry bit, such summation bit being fed to the memory for storage in such memory at the address provided by the address signal; and

(d) wherein such arithmetic unit includes a plurality of gates, each one of the gates having one input fed by the carry bit produced by a preceding one of the successively arranged adder sections and another input fed by a corresponding one of the bits of the carry bit mask, each one of such gates having an output coupled to the carry bit input of a succeeding one of the successively arranged adder section, each one of such gates passing, or inhibiting from passing, the carry bit fed thereto to the output thereof selectively in accordance with the carry bit coupled to the carry bit input thereof.