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System and method for assured built in self repair of memories

  • US 6,973,605 B1
  • Filed: 02/12/2002
  • Issued: 12/06/2005
  • Est. Priority Date: 06/15/2001
  • Status: Active Grant
First Claim
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1. A method for performing a high stress built-in self-repair for a memory, comprising the operations of:

  • providing an internal clock signal for use in accessing a memory array, the memory array having access to redundant memory cells during normal operation;

    performing a built-in self-test on the memory array at each power-up event using a stress clock signal, wherein the stress clock signal has a predetermined frequency greater than the internal clock signal, the predetermined frequency simulating functioning of the memory array under stressed environmental and operating conditions, and wherein the stress clock signal is not used during normal memory access operations;

    storing defective memory addresses detected by the built-in self-test in a memory block; and

    redirecting memory access operations to the defective memory addresses to redundant memory cells.

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