IC layouts with at least one layer that has more than one preferred interconnect direction, and method and apparatus for generating such a layout

• US 6,973,634 B1
• Filed: 08/26/2002
• Issued: 12/06/2005
• Est. Priority Date: 01/22/2002
• Status: Expired due to Fees

• Current Assignee: Cadence Design Systems Incorporated (Cadence Group)
• Original Assignee: Cadence Design Systems Incorporated (Cadence Group)
• Inventors: Teig, Steven, Caldwell, Andrew, Jacques, Etienne
• Primary Examiner(s): Smith, Matthew
• Assistant Examiner(s): Kik, Phallaka
• Application Number:
  US10/228,736
• Time in Patent Office: 1,198 Days
• Field of Search: 716/13, 716/14, 716/8, 326/41, 326/47, 326/101
• US Class Current: 716/129
• CPC Class Codes: G06F 30/394 Routing G06F30/396 takes precedence
• CPC Class Codes: H01L 23/528 Geometry or layout of the interconnection structure H01L27/0207 takes precedence; algorithms G06F30/00
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

Some embodiments of the invention provide a region of an integrated-circuit (“IC”) layout that has a plurality of interconnect layers, where at least one particular layer has more than one preferred interconnect direction. In some of these embodiments, the region has several interconnect layers that have more than one preferred wiring direction each.

Claims

1. A region of an integrated-circuit (“

IC”

) layout, the IC-layout region comprising a plurality of interconnect layers, wherein at least a particular layer has at least two preferred interconnect directions in that region, wherein in no part of the region on the particular layer are routes in either of the two preferred interconnect directions assessed a non-preferred direction routing penalty that results in one of the two preferred interconnect directions being more preferable than the other preferred interconnect direction.

2. The IC-layout region of claim 1, wherein each of a plurality of the interconnect layers has more than one preferred wiring direction.

3. The IC-layout region of claim 1, wherein the region represents an entire layout of an IC.

4. The IC-layout region of claim 1, wherein the region represents a portion of the IC layout.

12. The method of claim 1, wherein the wiring model specifies more than one preferred wiring directions for each interconnect layer of the region.

5. A region of an integrated-circuit (“

IC”

) layout, the IC-layout region comprising a plurality of interconnect layers, wherein at least a particular layer has more than one preferred interconnect direction, wherein a plurality of interconnect lines are on the particular layer, wherein at most 70% of the interconnect lines on the particular layer are in the same preferred direction.

6. The IC-layout region of claim 5, wherein the particular layer has two preferred wiring directions.

7. The IC-layout region of claim 6, wherein the two preferred wiring directions are horizontal and vertical directions.

8. The IC-layout region of claim 5, wherein the particular layer has four preferred wiring directions, and wherein at most 50% of the interconnect lines on the particular layer are in the same preferred direction.

9. The IC-layout region of claim 5, wherein the particular layer has four preferred wiring directions, and wherein at most 60% of the interconnect lines on the particular layer are in the same preferred direction.

10. A method of routing nets in a region of an integrated-circuit layout, the region having a plurality of interconnect layers, the method comprising:

a) receiving nets;

b) defining routes for nets by using a wiring model that specifies at least two preferred wiring directions for a particular interconnect layer of the region, wherein in no part of the region on the particular layer are routes in either of the two preferred interconnect directions assessed a non-preferred direction routing penalty that results in one of the two preferred interconnect directions being more preferable than the other preferred interconnect direction.

11. The method of claim 10, wherein the wiring model specifies more than one preferred wiring directions for each of a plurality of interconnect layers of the region.

13. The method of claim 10, wherein using the wiring model comprises costing routes in the preferred directions of the particular interconnect layer solely according to metric costs that the routes in these directions introduced in a design of an integrated circuit.

14. The method of claim 13, wherein costing the routes comprises using an identical unit cost to cost the routes in the preferred directions of the particular layer.

15. A computer readable medium comprising a computer program having executable code, the computer program for routing nets in a region of an integrated-circuit layout, the region having a plurality of interconnect layers, the computer program comprising sets of instructions for:

a) receiving nets;

b) defining routes for nets by using a wiring model that specifies at least two preferred wiring directions for a particular interconnect layer of the region, wherein in no part of the region on the particular layer are routes in either of the two preferred interconnect directions assessed a non-preferred direction routing penalty that results in one of the two preferred interconnect directions being more preferable than the other preferred interconnect direction.

16. The computer readable medium of claim 15, wherein the wiring model specifies more than one preferred wiring directions for each of a plurality of interconnect layers of the region.

17. The computer readable medium of claim 15, wherein the route have a plurality of paths on the particular layer, wherein the paths are in the preferred directions, wherein using the wiring model comprises costing the paths in the preferred directions solely according to metric costs that the paths in these directions introduced in a design of an integrated circuit.

18. The computer readable medium of claim 17, wherein costing the paths comprises using an identical unit cost to cost the routes in the preferred directions of the particular layer.