Isolation structures for imposing stress patterns

• US 6,974,981 B2
• Filed: 12/12/2002
• Issued: 12/13/2005
• Est. Priority Date: 12/12/2002
• Status: Active Grant

• Current Assignee: Globalfoundries US Incorporated (GlobalFoundries, Inc.)
• Original Assignee: International Business Machines Corporation
• Inventors: Chidambarrao, Dureseti, Doris, Bruce B., Dokumaci, Omer H., Mandelman, Jack A.
• Primary Examiner(s): Abraham, Fetsum
• Application Number:
  US10/318,600
• Publication Number:
  US 20040113174A1
• Time in Patent Office: 1,097 Days
• Field of Search: 257/374, 257/375, 438/207, 438/218
• US Class Current: 257/265
• CPC Class Codes: H01L 21/76232 of trenches having a shape other than rectangular or V-shape, e.g. rounded corners, oblique or rounded trench walls H01L21/76229 takes precedence
• CPC Class Codes: H01L 21/823807 with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
• CPC Class Codes: H01L 21/823878 isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure
• CPC Class Codes: H01L 29/7846 the means being located in the lateral device isolation region, e.g. STI
• CPC Class Codes: H01L 29/785 having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET

Abstract

A substrate under tension and/or compression improves performance of devices fabricated therein. Tension and/or compression can be imposed on a substrate through selection of appropriate STI fill material. The STI regions are formed in the substrate layer and impose forces on adjacent substrate areas. The substrate areas under compression or tension exhibit charge mobility characteristics different from those of a non-stressed substrate. By controllably varying these stresses within NFET and PFET devices formed on a substrate, improvements in IC performance are achieved.

Claims

1. An isolation structure for devices formed in a substrate, the devices each having a longitudinal direction and a transverse direction, the structure comprising:

a first isolation region for a first one of the devices, the first isolation region having therein a first isolation material which applies a first type of mechanical stress on the first one of the devices in the longitudinal direction and also in the transverse direction;

a second isolation region for a second one of the devices, the second isolation region having therein the first isolation material which applies the first type of mechanical stress on the second one of the devices in the transverse direction; and

a third isolation region for the second one of the devices, the third isolation region having therein a second isolation material which applies a second type of mechanical stress on the second one of the devices in the longitudinal direction,

wherein the first one of the devices is an NFET and the second one of the devices is a PFET, and

the first isolation material is TEOS and the second isolation material is HDP.

2. A method for making devices in a substrate, the devices each having sides extending in a longitudinal direction and ends extending in a transverse direction, the method comprising:

forming a first isolation region at the sides and at the ends of a first one of the devices;

providing a first isolation material in the first isolation region to apply a first type of mechanical stress on the first one of the devices in the longitudinal direction and in the transverse direction;

forming a second isolation region at the sides of a second one of the devices;

forming a third isolation region at the ends of the second one of the devices;

providing the first isolation material in the second isolation region to apply the first type of mechanical stress on the second one of the devices in the transverse direction; and

providing a second isolation material in the third isolation region to apply a second type of mechanical stress on the second one of the devices in the longitudinal direction,

wherein the first one of the devices is an NFET and the second one of the devices is a PFET, and

the first isolation material is TEOS and the second isolation material is HDP.