Semiconductor device with modified channel compressive stress

• US 6,975,006 B2
• Filed: 07/25/2003
• Issued: 12/13/2005
• Est. Priority Date: 07/25/2003
• Status: Expired due to Fees

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Yang, Fu-Liang, Huang, Chien-Chao, Huang, Cheng-Chuan, Chung, Tone-Xuan
• Primary Examiner(s): LE, DUNG ANH
• Application Number:
  US10/627,849
• Publication Number:
  US 20050019998A1
• Time in Patent Office: 872 Days
• Field of Search: 257412-413, 257/410, 257340-346, 257/387, 438/595, 438303-304, 438660-664, 438682-685
• US Class Current: 257/410
• CPC Class Codes: H01L 29/4983 with a lateral structure, e.g. a Polysilicon gate with a lateral doping variation or with a lateral composition variation or characterised by the sidewalls being composed of conductive, resistive or dielectric material
• CPC Class Codes: H01L 29/6656 using multiple spacer layers, e.g. multiple sidewall spacers
• CPC Class Codes: H01L 29/7842 means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate variation of the composition of the channel H01L29/1054
• CPC Class Codes: H01L 29/7843 the means being an applied insulating layer

Abstract

A semiconductor device includes a substrate and a gate region on top of a substrate. First and second gate sidewall liners are situated on first and second sides of the gate region respectively, the first and second sidewall liners having a vertical part contacting sidewalls of the gate region and a horizontal part contacting the substrate. First and second recessed spacers are situated on top of the first and second sidewall liners respectively. The height of the first and second spacers is lower than the height of the gate sidewall liner whereas the width of the horizontal part of the sidewall liner is shorter than the width of the spacer.

Claims

1. A semiconductor device comprising:

a substrate;

a gate region on top of the substrate;

a sidewall liner situated on a side of the gate region and having a vertical part contacting a sidewall of the gate region and a horizontal part contacting the substrate; and

a recessed spacer situated on top of the sidewall liner,

wherein a height of the recessed spacer is lower than a height of the sidewall liner,

wherein the horizontal part of the sidewall liner is shorter than the corresponding recessed spacer on top thereof; and

a contact etch stopping (CES) layer formed over the recessed spacer and having a predetermined stress level being one of compressive and tensile.

2. The device of claim 1 wherein the height of the recessed spacer is at least 50 Å

lower than the height of the vertical part of the sidewall liner.

3. The device of claim 1 wherein the horizontal part of each gate sidewall liner is at least 10 Å

shorter than the recessed spacer.

4. The device of claim 1 wherein the gate region further includes a gate dielectric and electrode layers.

5. The device of claim 4 wherein the height of the gate region does not exceed 1800 Å

.

6. The device of claim 1 wherein the recessed spacer is SiN based.

7. The device of claim 1 wherein the recessed spacer further includes Ge, Ar, or O₂ based impurities.

8. The device of claim 1 wherein the sidewall liner is oxide based.

9. The device of claim 1 wherein the CES layer imposes a compressive stress.

10. The device of claim 1 wherein the CES layer imposes a tensile stress.

11. The device of claim 1 wherein the stress level of contact etching stopper layer is larger than 200 M Pa.

12. The device of claim 1 wherein the thickness of the CES layer is smaller than 600 Å

.