Semiconductor device

• US 6,975,142 B2
• Filed: 04/17/2002
• Issued: 12/13/2005
• Est. Priority Date: 04/27/2001
• Status: Active Grant

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: Nagao, Shou, Tanada, Yoshifumi, Azami, Munehiro
• Primary Examiner(s): Tan, Vibol
• Application Number:
  US10/123,251
• Publication Number:
  US 20020158666A1
• Time in Patent Office: 1,336 Days
• Field of Search: 326/83, 326/88, 326/119, 326/81, 327/390, 257/72, 257/350, 345 98-100, 345204-206, 345211-213
• US Class Current: 326/88
• CPC Class Codes: H01L 29/786 Thin film transistors, i.e. transistors with a channel being at least partly a thin film transistors having only the source or the drain region on an insulator layer H01L29/0653; thin film FinFETs H01L29/785
• CPC Class Codes: H03K 19/01714 by bootstrapping, i.e. by positive feed-back
• CPC Class Codes: H03K 19/01721 by means of a pull-up or down element

Abstract

There is provided a semiconductor device in which fabrication steps can be reduced by constructing a circuit using only TFTs of one conductivity type and in which a voltage amplitude of an output signal can be normally obtained. A capacitance (205) is provided between a gate and a source of a TFT (203) connected to an output node, and a circuit formed of TFTs (201) and (202) has a function to bring a node a into a floating state. When the node α is in the floating state, a potential of the node a is caused higher than VDD by using gate-source capacitance coupling of the TFT (203) through the capacitance (205), thus an output signal having an amplitude of VDD-GND can be normally obtained without causing amplitude attenuation due to the threshold value of the TFT.

Claims

1. A semiconductor device comprising:

a first thin film transistor having a first impurity region electrically connected to a first power source;

a second thin film transistor having a first impurity region electrically connected to a second power source;

a third thin film transistor having a first impurity region electrically connected to the first power source;

a fourth thin film transistor having a first impurity region electrically connected to the second power source,

wherein;

the first to fourth thin film transistors have a same conductivity type;

a second impurity region of the first thin film transistor and a second impurity region of the second thin film transistor are electrically connected to one terminal of a capacitance;

a second impurity region of the third thin film transistor, a second impurity region of the fourth thin film transistor, and a gate electrode of the first thin film transistor are electrically connected to the other terminal of the capacitance;

a gate electrode of the second thin film transistor and a gate electrode of the fourth thin film transistor are electrically connected to a first input signal line; and

a gate electrode of the third thin film transistor is electrically connected to a second input signal line.

2. The semiconductor device according to claim 1, wherein the second input signal line is the signal line to which an inversion signal of a signal inputted to the first input signal line is inputted.

3. The semiconductor device according to claim 1, wherein the capacitance uses a capacitance between the gate electrode of the first thin film transistor and one of the impurity regions.

4. The semiconductor device according to claim 1, wherein the capacitance is a capacitance constituted by using any two materials of an active layer material, a material forming the gate electrodes, and a wiring material.

5. The semiconductor device according to claim 1, wherein the one conductivity is an N-channel type.

6. The semiconductor device according to claim 1, wherein the one conductivity is a P-channel type.

7. The semiconductor device according to claim 1, wherein:

the one conductivity is an N-channel type;

a potential at a time when the input signal is at an H level is equal to a third power source potential, and a potential at a time when the input signal is at an L level is equal to a fourth power source potential; and

a relation of a second power source potential≦

the fourth power source potential<

the third power source potential≦

a first power source potential is satisfied.

8. The semiconductor device according to claim 1, wherein:

the one conductivity is a P-channel type;

a potential at a time when the input signal is at a H level is equal to a third power source potential, and a potential at a time when the input signal is at a L level is equal to a fourth power source potential; and

a relation of a first power source potential≦

the fourth power source potential<

the third power source potential≦

a second power source potential is satisfied.

9. The semiconductor device according to claim 1, wherein the semiconductor device is one selected from the group consisting of an inverter, a buffer, and a level shifter.

10. The semiconductor device according to claim 1, wherein the semiconductor device is applied to an electronic equipment selected from the group consisting of a liquid crystal display, a video camera, a notebook personal computer, a portable information terminal, an on-vehicle audio apparatus, a digital camera and a portable telephone.

11. A display device having at least one driving circuit, the driving circuit comprising:

a first thin film transistor having a first impurity region electrically connected to a first power source;

a second thin film transistor having a first impurity region electrically connected to a second power source;

a third thin film transistor having a first impurity region electrically connected to the first power source;

a fourth thin film transistor having a first impurity region electrically connected to the second power source, wherein;

the first to fourth thin film transistors have a same conductivity type;

a second impurity region of the first thin film transistor and a second impurity region of the second thin film transistor are electrically connected to one terminal of a capacitance;

a second impurity region of the third thin film transistor, a second impurity region of the fourth thin film transistor, and a gate electrode of the first thin film transistor are electrically connected to the other terminal of the capacitance;

a gate electrode of the second thin film transistor and a gate electrode of the fourth thin film transistor are electrically connected to a first input signal line; and

a gate electrode of the third thin film transistor is electrically connected to a second input signal line.

12. A semiconductor device comprising:

a first thin film transistor having a first impurity region electrically connected to a first power source;

a second thin film transistor having a first impurity region electrically connected to a second power source;

a third thin film transistor having a first impurity region electrically connected to the first power source;

a fourth thin film transistor having a first impurity region electrically connected to the second power source,

wherein;

the first to fourth thin film transistors have a same conductivity type;

a second impurity region of the first thin film transistor and a second impurity region of the second thin film transistor are electrically connected to output signal line;

a second impurity region of the third thin film transistor and a second impurity region of the fourth thin film transistor are electrically connected to a gate electrode of the first thin film transistor;

a gate electrode of the second thin film transistor and a gate electrode of the fourth thin film transistor are electrically connected to a first input signal line; and

a gate electrode of the third thin film transistor is electrically connected to a second input signal line.

13. A display device having at least one driving circuit, the driving circuit comprising:

a first thin film transistor having a first impurity region electrically connected to a first power source;

a second thin film transistor having a first impurity region electrically connected to a second power source;

a third thin film transistor having a first impurity region electrically connected to the first power source;

a fourth thin film transistor having a first impurity region electrically connected to the second power source, wherein;

the first to fourth thin film transistors have a same conductivity type;

a second impurity region of the first thin filxn transistor and a second impurity region of the second thin film transistor are electrically connected to output signal line;

a second impurity region of the third thin film transistor and a second impurity region of the fourth thin film transistor are electrically connected to a gate electrode of the first thin film transistor;

a gate electrode of the second thin film transistor and a gate electrode of the fourth thin film transistor are electrically connected to a first input signal line; and

a gate electrode of the third thin film transistor is electrically connected to a second input signal line.

14. A semiconductor device comprising:

a first thin film transistor having a first impurity region electrically connected to a first power source;

a second thin film transistor having a first impurity region electrically connected to a second power source;

an output amplitude compensating circuit having an input terminal and an output terminal, wherein the output terminal is electrically connected to a gate electrode of the first thin film transistor,

wherein;

channel forming regions of the first and second thin film transistors have a same conductivity type;

a second impurity region of the first thin film transistor and a second impurity region of the second thin film transistor are electrically connected to an output signal line;

a gate electrode of the second thin film transistor and the input terminal of the output amplitude compensating circuit are electrically connected to an input signal line.

15. The semiconductor device according to claim 14 wherein the output amplitude compensating circuit comprising:

a third thin film transistor having a first impurity region electrically connected to the first power source; and

a fourth thin film transistor having a first impurity region electrically connected to the second power source.

16. The semiconductor device according to claim 15 wherein a gate electrode of the third thin film transistor is electrically connected to a first impurity region of the third thin film transistor.

17. The semiconductor device according to claim 15 wherein a gate electrode of the fourth thin film transistor is electrically connected to the input signal line.

18. The semiconductor device according to claim 15 wherein a second impurity region of the third thin film transistor and a second impurity region of the fourth thin film transistor is electrically connected to the gate electrode of the first thin film transistor.

19. A display device comprising:

a first thin film transistor having a first impurity region electrically connected to a first power source;

a second thin film transistor having a first impurity region electrically connected to a second power source;

an output amplitude compensating circuit having an input terminal and an output terminal, wherein the output terminal is electrically connected to a gate electrode of the first thin film transistor,

wherein;

channel forming regions of the first and second thin film transistors have a same conductivity type;

a second impurity region of the first thin film transistor and a second impurity region of the second thin film transistor are electrically connected to an output signal line;

a gate electrode of the second thin film transistor and the input terminal of the output amplitude compensating circuit are electrically connected to an input signal line.

20. The display device according to claim 19 the output amplitude compensating circuit comprising:

a third thin film transistor having a first impurity region electrically connected to the first power source; and

a fourth thin film transistor having a first impurity region electrically connected to the second power source.

21. The display device according to claim 20 wherein a gate electrode of the third thin film transistor is electrically connected to a first impurity region of the third thin film transistor.

22. The display device according to claim 20 wherein a gate electrode of the fourth thin film transistor is electrically connected to the input signal-light.

23. The display device according to claim 20 wherein a second impurity region of the third thin film transistor and a second impurity region of the fourth thin film transistor is electrically connected to the gate electrode of the first thin film transistor.