Embedded inductor and method of making

• US 6,975,199 B2
• Filed: 12/13/2001
• Issued: 12/13/2005
• Est. Priority Date: 12/13/2001
• Status: Expired due to Term

• Current Assignee: Globalfoundries US Incorporated (GlobalFoundries, Inc.)
• Original Assignee: International Business Machines Corporation
• Inventors: Pillai, Edward R., Bhatia, Harsaran S., Long, David Clifford, Hamel, Harvey Charles, Tongue, Benjamin Paul, Setzer, Christopher David
• Primary Examiner(s): MAI, ANH T
• Application Number:
  US10/016,090
• Publication Number:
  US 20030112114A1
• Time in Patent Office: 1,461 Days
• Field of Search: 336/200, 336/232, 336/223, 296/021
• US Class Current: 336/200
• CPC Class Codes: H01F 17/0013 with stacked layers
• CPC Class Codes: H01F 17/0033 with the coil helically wound around a magnetic core
• CPC Class Codes: H01F 5/003 Printed circuit coils
• CPC Class Codes: H01L 27/08 including only semiconductor components of a single kind

Abstract

A dielectric substrate having an embedded inductor wherein each turn of the inductor traverses several layers such that the top and bottom of each turn of the inductor are parallel to each other but are in different layers and the sides of each turn of the inductor traverse at least one layer to connect the top and bottom of the inductor.

Claims

1. A dielectric substrate having a multiturn inductor comprising:

a) a multilayer dielectric body comprising a plurality of layers;

b) a multiturn inductor buried within the dielectric body, each turn of the inductor comprising a bottom portion, a top portion and two side portions, the bottom portion and top portion being parallel and in different layers of the dielectric body, the side portions being parallel to each other and extending between the top and bottom portions and comprising vias in the dielectric body, wherein the top and bottom portions have a lower crossectional area than the side portions and wherein the top and bottom portions each comprise two parallel wiring lines in juxtaposition.

2. The dielectric substrate of claim 1 wherein the top and bottom portions comprise wiring lines situated in respective layers of the dielectric body.

3. The dielectric substrate of claim 1 wherein the turns of the multiturn inductor form a toroidal shape.

4. The dielectric substrate of claim 1 wherein to multiturn inductor is tuned by the addition of at least one additional buried loop to the multiturn inductor.

5. The dielectric substrate of claim 1 wherein the multiturn inductor is tuned by the addition of a plate adjacent to the multiturn inductor, the plate being electrically isolated from the multiturn inductor.

6. The dielectric substrate of claim 1 wherein the multiturn inductor is tuned by the addition of a plate adjacent to the multiturn inductor, the plate being electrically connected to the multiturn inductor.

7. The dielectric substrate of claim 1 wherein the multiturn inductor is a first multiturn inductor and further comprising a second buried multiturn inductor near the first multiturn inductor but electrically isolated therefrom, the first and second multiturn inductors cooperating to form a transformer.

8. The dielectric substrate of claim 1 wherein the multiturn inductor is tuned by tapping the multiturn inductor at selected locations.

9. The dielectric substrate of claim 8 further comprising deletion of a portion of the multiturn inductor so as to tune the multiturn inductor.

10. The dielectric substrate of claim 1 further comprising vias connecting the parallel wiring lines of each of the top and bottom portions.

11. The dielectric substrate of claim 10 wherein the parallel wiring lines have ends and wherein the vias connecting the parallel wiring lines are only at the ends of the lines.

12. The dielectric substrate of claim 10 wherein the parallel wiring lines each have a length and wherein the vias connecting the parallel wiring lines are spaced along the length of the parallel wiring lines.

13. The dielectric substrate of claim 1 wherein the top and bottom portions are planar in shape so as to comprise a flat portion having a width and a thickness less than the width, the side portions having a circular contact surface and the flat portion of the top and bottom portions in contact with the circular contact surface of the side portion.

14. The dielectric substrate of claim 1 wherein the top and bottom portions are planar wiring lines and the side portions are visa having a circular contact surface wherein the planar wiring lines directly contact the circular contact surface of the vias.

15. A dielectric substrate having a multiturn inductor comprising:

a) a multilayer dielectric body comprising a plurality of layers;

b) a multiturn inductor buried within the dielectric body, each turn of the inductor comprising a bottom portion, a top portion and two side portions, the bottom portion and top portion being parallel and in different layers of the dielectric body, the side portions being parallel to each other and extending between the top and bottom portions and comprising vias in the dielectric body, wherein the top and bottom portions have a lower crossectional area than the side portions and wherein the top and bottom portions each comprise at least two parallel wiring lines of unequal length in juxtaposition.