System for digitizing transient signals with waveform accumulator

• US 6,975,251 B2
• Filed: 08/24/2004
• Issued: 12/13/2005
• Est. Priority Date: 06/20/2002
• Status: Expired due to Fees

• Current Assignee: Fluorescence Innovations, Inc.
• Original Assignee: Dakota Technologies, Inc.
• Inventors: Pavicic, Mark J.
• Primary Examiner(s): Jeanglaude, Jean Bruner
• Application Number:
  US10/924,405
• Publication Number:
  US 20050024249A1
• Time in Patent Office: 476 Days
• Field of Search: 341/50, 341/155, 341/122, 341/166, 345/440.1
• US Class Current: 341/50
• CPC Class Codes: H03M 1/123 Simultaneous, i.e. using one converter per channel but with common control or reference circuits for multiple converters
• CPC Class Codes: H03M 1/127 at intervals varying with the rate of change of the input signal
• CPC Class Codes: H03M 1/56 Input signal compared with linear ramp

Abstract

An apparatus for capturing and digitizing a signal derived from an event has a memory for storing a sequence of analog samples from the signal derived from the event in a sampling operation occurring at about a 0.5 gigahertz or higher sampling rate. Circuitry communicating with the memory selectively initiates the read out of the analog samples in the memories. An array of analog to digital converters receives a sequence of analog samples read out from the memory and produces from the analog samples a corresponding vector of digitized sample values. A waveform accumulator integrated with the array of analog to digital converters receives a vector of digitized sample values from a new waveform and combines these with a vector of digitized sample values from at least one prior waveform. An output stage outputs the vector of digitized sample values developed in the waveform accumulator.

Claims

1. An apparatus for capturing and digitizing a signal derived from an event, comprising:

a memory for storing a sequence of analog samples from the signal derived from the event in a sampling operation occurring at about a 0.5 gigahertz or higher sampling rate;

means communicating with the memory for selectively initiating the read out of analog samples in the memory;

an array of analog to digital converters for receiving a sequence of analog samples read out from the memory and producing from the analog samples a corresponding vector of digitized sample values;

a waveform accumulator integrated with the array of analog to digital converters for receiving a vector of new digitized sample values from a new sampling operation and combining these with a vector of digitized sample values from at least one prior sampling operation; and

an output stage for outputting the digitized sample values developed in the waveform accumulator.

2. The apparatus of claim 1 wherein the memory and array of analog to digital converters with waveform accumulator are all integrated on one chip.

3. The apparatus of claim 2 wherein the chip is a CMOS or bi-CMOS chip.

4. The apparatus of claim 1 wherein the apparatus is configured to alternately store analog samples and to convert and combine the digitized sample values, with the time for converting and combining being less than or approximately equal to the time for storing.

5. The apparatus of claim 1 wherein the waveform accumulator comprises sample processing units configured to use a ripple technique for combining the digitized sample values from the new and at least one prior sampling operation.

6. The apparatus of claim 5, wherein the ripple technique uses Gray to binary conversion and binary addition for combining the digitized sample values.

7. The apparatus of claim 1 wherein the waveform accumulator comprises an array of sample processing units with single-bit logic elements interleaved with single-bit storage elements.

8. The apparatus of claim 1 wherein the waveform accumulator comprises two or more waveform accumulator registers and control circuitry to permit selection of one of the two or more waveform accumulator registers for combining the vectors of digitized sample values from the new and at least one prior sampling operation.

9. The apparatus of claim 1 wherein the waveform accumulator comprises sample processing units and each sample processing unit comprises an ALU for use in processing digitized sample values.

10. The apparatus of claim 1 wherein the memory is capable of storing multiple vectors of analog samples to define a matrix and wherein the vectors of analog samples appear as rows of the matrix and the means for read out selectively initiates read out of the samples by selecting a row of analog samples for read out.

11. A method for capturing and digitizing a signal derived from an event, comprising:

storing at about a 0.5 gigahertz or higher rate in a memory analog waveform samples of the signal derived from the event;

selectively initiating the read out of the analog samples in the memory;

receiving at an array of analog to digital converters analog samples read out from the memory and producing for the analog samples in the memory a corresponding vector of digitized sample values;

controlling a waveform accumulator integrated with the array of analog to digital converters to receive a vector of digitized sample values from a new waveform and to combine the vector of digitized sample values from the new waveform with a vector of digitized sample values from at least one prior waveform; and

outputting the combined vector of digitized sample values from the waveform accumulator.

12. The method of claim 11 wherein the step of outputting the combined digitized sample values comprises outputting the digitized sample values to a port of a digital signal processor integrated with the memory and the waveform accumulator.

13. The method of claim 11 wherein the step of controlling a waveform accumulator comprises performing Gray to binary conversion of the vector of digitized sample values of the new waveform and combining these digitized sample values with digitized sample values of the at least one prior waveform.

14. The method of claim 11 further comprising controlling the outputting step so that the number of waveforms accumulated is a selectable parameter.

15. The method of claim 11 further comprising controlling the outputting step responsive to a “

full”

signal from the waveform accumulator to determine a desired waveform accumulation level.

16. The method of claim 11 wherein the memory is capable of storing multiple vectors of analog samples and the storing step comprises storing analog samples to define a matrix with the vectors of analog samples appearing as rows and the selectively initiating step comprises selecting a row of analog samples for read out.

17. An apparatus for capturing and digitizing analog samples derived from a waveform representing an event, comprising:

a memory capable of storing a vector of analog samples from the waveform, sampled at approximately a 0.5 gigahertz or higher rate;

a digital signal processor;

control means associated with the digital signal processor for communicating with the memory and for selectively initiating the read out of the vector of analog samples in the memory;

an array of analog to digital converters for receiving the vector of analog samples read out from the memory and producing a corresponding vector of digitized sample values;

a waveform accumulator under control of the digital signal processor and coupled to the array of analog to digital converters for receiving a vector of digitized sample values from a new waveform and combining these with a vector of digitized sample values of at least one prior waveform; and

an output stage under control of the digital signal processor for controlling the waveform combining and outputting the digitized sample values combined in the waveform accumulator after a specified accumulation level is reached.

18. The apparatus of claim 17 wherein the waveform accumulator comprises circuitry for Gray to binary conversion of the vector of digitized sample values of the new waveform and combining these digitized sample values with the vector of digitized sample values of the at least one prior waveform.

19. The apparatus of claim 17 wherein the digital signal processor controls the number of waveforms accumulated as a predetermined selectable parameter.

20. The apparatus of claim 17 wherein the digital signal processor monitors a “

full”

signal from the waveform accumulator and determines a desired accumulation level responsive to the “

full”

signal.

21. The apparatus of claim 17 wherein the waveform accumulator comprises sample processing units configured to use a ripple technique for combining the digitized sample values from the new waveform and at least one prior waveform.

22. The apparatus of claim 17 wherein the memory is capable of storing multiple vectors of analog samples to define a matrix and wherein the vectors of analog samples appear as rows of the matrix and the control means selectively initiates read out of the samples by selecting a row of analog samples for read out.