Video and graphics system with a video transport processor

• US 6,975,324 B1
• Filed: 08/18/2000
• Issued: 12/13/2005
• Est. Priority Date: 11/09/1999
• Status: Expired due to Fees

• Current Assignee: Avago Technologies General IP PTE Limited (Broadcom, Inc.)
• Original Assignee: Broadcom Corporation (Broadcom, Inc.)
• Inventors: Bhatia, Sandeep, Valmiki, Ramanujan K.
• Primary Examiner(s): Bella, Matthew C.
• Assistant Examiner(s): Sajous, Wesner
• Application Number:
  US09/641,930
• Time in Patent Office: 1,943 Days
• Field of Search: 345/619, 345/629, 345/630, 345/751, 345716-721, 345501-503, 345/601, 345519-520, 345/547, 345/556, 345/567, 345571-574, 348563-569, 348/715, 348/714, 380209-210, 380/212, 380/217, 725 63- 66, 725/68, 725/71, 725/115, 725141-143, 370/326, 370/336, 370342-345, 370349-350, 370/481, 370441-442, 370532-542, 370/335, 375/240.01, 715716-721
• US Class Current: 345/555
• CPC Class Codes: G09G 2340/0414 Vertical resolution change
• CPC Class Codes: G09G 2340/0421 Horizontal resolution change
• CPC Class Codes: G09G 2340/0435 Change or adaptation of the frame rate of the video stream
• CPC Class Codes: G09G 2340/10 Mixing of images, i.e. displayed pixel being the result of an operation, e.g. adding, on the corresponding input pixels
• CPC Class Codes: G09G 2340/125 wherein one of the images is motion video
• CPC Class Codes: G09G 2360/125 using unified memory architecture [UMA]
• CPC Class Codes: G09G 2360/126 The frame memory having additional data ports, not inclusive of standard details of the output serial port of a VRAM
• CPC Class Codes: G09G 5/06 using colour palettes, e.g. look-up tables
• CPC Class Codes: G09G 5/14 Display of multiple viewports
• CPC Class Codes: G09G 5/39 Control of the bit-mapped memory
• CPC Class Codes: H04N 19/426 using memory downsizing methods
• CPC Class Codes: H04N 19/436 using parallelised computational arrangements
• CPC Class Codes: H04N 19/59 involving spatial sub-sampling or interpolation, e.g. alteration of picture size or resolution
• CPC Class Codes: H04N 19/61 in combination with predictive coding
• CPC Class Codes: H04N 21/42653 for processing graphics
• CPC Class Codes: H04N 21/42692 for reading from or writing on a volatile storage medium, e.g. Random Access Memory [RAM]
• CPC Class Codes: H04N 21/4305 Synchronising client clock from received content stream, e.g. locking decoder clock with encoder clock, extraction of the PCR packets arrangements for synchronising receiver with transmitter by comparing receiver clock with transmitter clock H04L7/0012; arrangements for synchronising receiver with transmitter wherein the receiver takes measures against momentary loss of synchronisation H04L7/0083
• CPC Class Codes: H04N 21/4316 for displaying supplemental content in a region of the screen, e.g. an advertisement in a separate window
• CPC Class Codes: H04N 21/4345 Extraction or processing of SI, e.g. extracting service information from an MPEG stream
• CPC Class Codes: H04N 21/4348 Demultiplexing of additional data and video streams
• CPC Class Codes: H04N 21/440218 : by transcoding between formats or standards, e.g. from MPEG-2 to MPEG-4 conversion of standards in analogue television systems H04N7/01
• CPC Class Codes: H04N 21/4435 : Memory management allocation of memory to service a request G06F9/5016; addressing or allocating within memory systems or architectures G06F12/02
• CPC Class Codes: H04N 5/44504 : Circuit details of the additional information generator, e.g. details of the character or graphics signal generator, overlay mixing circuits
• CPC Class Codes: H04N 5/45 : Picture in picture , e.g. displaying simultaneously another television channel in a region of the screen
• CPC Class Codes: H04N 7/01 : Conversion of standards , e.g. involving analogue television standards or digital television standards processed at pixel level
• CPC Class Codes: H04N 7/0135 : involving interpolation processes interpolation-based image scaling G06T3/4007; interpolation for video coding H04N19/587, H04N19/59

Abstract

A video and graphics system includes a data transport processor for receiving compressed data streams, a video transport processor for extracting video data, and an audio decode processor for extracting audio data. The data transport processor provides PCRs to the video transport processor and the audio decode processor. The video transport-processor stores the video data in external memory and generates a start code table to index the video data stored the external memory. In the start code table SLICEs of the video data are aligned to a suitable boundary. The compressed data streams may include MPEG Transport streams, and the video data may include SDTV or HDTV data. The video and graphics system may be implemented on an integrated circuit chip.

Claims

1. A system comprising:

a core transport processor for receiving a plurality of compressed data streams;

a first satellite transport processor for receiving at least one of the compressed data streams and extracting video data; and

a second satellite transport processor for receiving at least one of the compressed data streams and extracting audio data,

wherein the core transport processor provides data related to the compressed data streams to at least one of the first satellite transport processor and the second satellite transport processor,

wherein the first satellite transport processor stores the video data in a memory block and generates a start code table to index the video data stored in the memory block,

wherein the plurality of compressed data streams include at least one MPEG-2 Transport stream, and

wherein the video data includes a plurality of SLICEs, and the start code table is used to index the video data, SLICE by SLICE.

2. The system of claim 1 wherein the core transport processor, the first satellite transport processor and the second satellite transport processor are integrated on an integrated circuit chip.

3. The system of claim 1 wherein the data related to the compressed data streams include clock reference data.

4. The system of claim 1 wherein said at least one MPEG-2 Transport stream includes at least one in-band stream and at least one out-of-band stream.

5. The system of claim 1 further comprising an MPEG-2 video decoder for reading the video data from the memory block and decoding the video data.

6. The system of claim 1 wherein the plurality of SLICEs include a plurality of rows of video data in the memory block, and the start code table is used to index the video data, row by row.

7. The system of claim 1 wherein the first satellite transport processor aligns the start of each of the plurality of SLICEs to a suitable boundary in the memory block when storing the video data in the memory block.

8. The system of claim 1 wherein the first satellite transport processor processes down to and including a SLICE layer of said at least one MPEG-2 Transport stream.

9. The system of claim 1 wherein the video data includes at least one HDTV video.

10. A method of processing a plurality of transport streams using a system with multiple transport processors comprising the steps of:

receiving a plurality of compressed data streams at a core transport processor;

receiving at least one of the plurality of compressed data streams at a first satellite transport processor, and extracting video data;

receiving at least one of the plurality of compressed data streams at a second satellite transport processor, and extracting audio data;

transferring data related to the compressed data streams from the core transport processor to at least one of the first satellite transport processor and the second satellite transport processor;

storing the video data in a memory block; and

generating a start code table to index the video data stored in the memory block,

wherein the step of receiving the plurality of compressed data streams comprises the step of receiving at least one MPEG-2 Transport stream, and

wherein the step of reading the video data includes the step of indexing the video data, SLICE by SLICE.

11. The method of processing a plurality of transport streams of claim 10 wherein the step of transferring data related to the compressed data streams comprises the step of transferring clock reference data.

12. The method of processing a plurality of transport streams of claim 10 wherein the step of receiving at least one MPEG-2 Transport stream comprises the steps of receiving at least one in-band stream and receiving at least one out-of-band stream.

13. The method of processing a plurality of transport streams of claim 10 further comprising the steps of reading the video data from the memory block and decoding the video data.

14. The method of processing a plurality of transport streams of claim 10 wherein the step of extracting video data comprises the step of extracting at least one HDTV video.

15. A method of processing a plurality of transport streams using a system with multiple transport processors comprising the steps of:

receiving a plurality of compressed data streams at a core transport processor;

receiving at least one of the plurality of compressed data streams at a first satellite transport processor, and extracting video data;

receiving at least one of the plurality of compressed data streams at a second satellite transport processor, and extracting audio data;

transferring data related to the compressed data streams from the core transport processor to at least one of the first satellite transport processor and the second satellite transport processor;

storing the video data in a memory block;

generating a start code table to index the video data stored in the memory block;

reading the video data from the memory block; and

decoding the video data,

wherein the step of receiving the plurality of compressed data streams comprises the step of receiving at least one MPEG-2 Transport stream, and

wherein the video data is stored in the memory block as rows, and the step of reading the video data includes the step of indexing the video data, row by row.

16. A method of processing a plurality of transport streams using a system with multiple transport processors comprising the steps of:

receiving a plurality of compressed data streams at a core transport processor;

receiving at least one of the plurality of compressed data streams at a first satellite transport processor, and extracting video data;

receiving at least one of the plurality of compressed data streams at a second satellite transport processor, and extracting audio data;

transferring data related to the compressed data streams from the core transport processor to at least one of the first satellite transport processor and the second satellite transport processor;

storing the video data in a memory block; and

generating a start code table to index the video data stored in the memory block,

wherein the step of storing the video data comprises the step of aligning a start of each of the plurality of SLICEs to a suitable boundary in the memory block.

17. A system comprising:

a core transport processor for receiving a plurality of compressed data streams;

a satellite transport processor for receiving at least one of the compressed data streams and for extracting video data, the video data including a plurality of SLICEs;

an MPEG-2 video decoder for decoding the video data to generate decoded video data; and

a video compositor for blending the decoded video data with graphics,

wherein the satellite transport processor generates a start code table to index the video data and aligns the plurality of SLICEs to a suitable boundary in an external memory.

18. The system of claim 17 wherein the core transport processor, the satellite transport processor, the MPEG-2 video decoder and the video compositor are integrated on an integrated circuit chip.

19. The system of claim 17 wherein the video data include SDTV video data.

20. The system of claim 17 wherein the video data include HDTV video data.

21. A video transport processor comprising:

an input for receiving an MPEG Transport stream including MPEG video data comprising a plurality of SLICEs;

a transport processor for processing headers in the MPEG Transport stream;

a start code alignment module for storing the MPEG video data in an external memory, for aligning a start of the plurality of SLICEs to a suitable boundary in the external memory when storing the MPEG video data in the external memory, and for generating a start code table to index the MPEG video data stored in the external memory; and

a switch for providing the MPEG Transport stream to the transport processor or the start code alignment module.

22. The video transport processor of claim 21, wherein the switch provides the MPEG Transport stream first to the transport processor, and provides the MPEG Transport stream to the start code alignment module after one or more headers have been processed.

23. A video transport processor comprising:

an input for receiving an MPEG Transport stream including MPEG video data comprising a plurality of SLICEs;

a transport processor for processing headers in the MPEG Transport stream; and

a start code alignment module for storing the MPEG video data in an external memory, for aligning a start of the plurality of SLICEs to a suitable boundary in the external memory when storing the MPEG video data in the external memory, and for generating a start code table to index the MPEG video data stored in the external memory,

wherein one or more zeros are added to at least one of the SLICEs to align another one of the SLICEs to the suitable boundary in the external memory.