Integrated circuit device

• US 6,975,558 B2
• Filed: 09/14/2004
• Issued: 12/13/2005
• Est. Priority Date: 04/18/1990
• Status: Expired due to Fees

• Current Assignee: Rambus Inc.
• Original Assignee: Rambus Inc.
• Inventors: Horowitz, Mark, Farmwald, Michael
• Primary Examiner(s): NGUYEN, TAN
• Application Number:
  US10/939,500
• Publication Number:
  US 20050033903A1
• Time in Patent Office: 455 Days
• Field of Search: 365/233, 365/194, 365/189.02, 365/230.02
• US Class Current: 365/233.16
• CPC Class Codes: G06F 11/006 Identification G06F11/2289 takes precedence
• CPC Class Codes: G06F 11/1048 using arrangements adapted for a specific error detection or correction feature
• CPC Class Codes: G06F 12/0215 with look ahead addressing means
• CPC Class Codes: G06F 12/0661 and decentralised selection
• CPC Class Codes: G06F 12/0684 with feedback, e.g. presence or absence of unit detected by addressing, overflow detection
• CPC Class Codes: G06F 13/1605 based on arbitration arbitration in handling access to a common bus or bus system G06F13/36
• CPC Class Codes: G06F 13/161 with latency improvement
• CPC Class Codes: G06F 13/1678 using bus width
• CPC Class Codes: G06F 13/1689 Synchronisation and timing concerns synchronisation on a memory bus G06F13/4234
• CPC Class Codes: G06F 13/1694 Configuration of memory controller to different memory types
• CPC Class Codes: G06F 13/376 using a contention resolving method, e.g. collision detection, collision avoidance
• CPC Class Codes: G06F 13/4239 with asynchronous protocol
• CPC Class Codes: G11C 11/4076 Timing circuits for regeneration management G11C11/406
• CPC Class Codes: G11C 11/4096 Input/output [I/O] data management or control circuits, e.g. reading or writing circuits, I/O drivers or bit-line switches
• CPC Class Codes: G11C 2207/105 Aspects related to pads, pins or terminals
• CPC Class Codes: G11C 2207/108 Wide data ports
• CPC Class Codes: G11C 29/88 with partially good memories
• CPC Class Codes: G11C 5/00 Details of stores covered by group G11C11/00
• CPC Class Codes: G11C 5/04 Supports for storage elements , e.g. memory modules; Mounting or fixing of storage elements on such supports
• CPC Class Codes: G11C 5/06 Arrangements for interconnecting storage elements electrically, e.g. by wiring
• CPC Class Codes: G11C 5/063 : Voltage and signal distribution in integrated semi-conductor memory access lines, e.g. word-line, bit-line, cross-over resistance, propagation delay
• CPC Class Codes: G11C 5/066 : Means for reducing external access-lines for a semiconductor memory clip, e.g. by multiplexing at least address and data signals
• CPC Class Codes: G11C 7/1006 : Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor
• CPC Class Codes: G11C 7/1012 : Data reordering during input/output, e.g. crossbars, layers of multiplexers, shifting or rotating
• CPC Class Codes: G11C 7/1045 : Read-write mode select circuits
• CPC Class Codes: G11C 7/1051 : Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
• CPC Class Codes: G11C 7/1057 : Data output buffers, e.g. comprising level conversion circuits, circuits for adapting load
• CPC Class Codes: G11C 7/1066 : Output synchronization
• CPC Class Codes: G11C 7/1069 : I/O lines read out arrangements
• CPC Class Codes: G11C 7/1072 : for memories with random access ports synchronised on clock signal pulse trains, e.g. synchronous memories, self timed memories
• CPC Class Codes: G11C 7/1078 : Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
• CPC Class Codes: G11C 7/1084 : Data input buffers, e.g. comprising level conversion circuits, circuits for adapting load
• CPC Class Codes: G11C 7/22 : Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management
• CPC Class Codes: G11C 7/222 : Clock generating, synchronizing or distributing circuits within memory device
• CPC Class Codes: G11C 7/225 : Clock input buffers
• CPC Class Codes: G11C 8/00 : Arrangements for selecting an address in a digital store for stores using transistors G11C11/407, G11C11/413
• CPC Class Codes: Y02D 10/00 : Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

An integrated circuit device is disclosed. In one particular exemplary embodiment, the integrated circuit device may comprise a first circuit to receive, in a multiplexed format, control information and address information, wherein the control information specifies a write operation and the address information specifies a location within a memory array for the write operation. The integrated circuit device may also comprise a second circuit that includes a plurality of output drivers to output write data to be written to the memory array during the write operation, wherein the write data is output after a number of clock cycles of an external clock signal transpire, wherein the write data is output in response to the control information, and wherein each output driver of the plurality of output drivers outputs two bits of the write data during a single clock cycle of the external clock signal.

Claims

1. An integrated circuit comprising:

a first circuit to receive, in a multiplexed format, control information and address information, the control information specifying a write operation, and the address information specifying a location within a memory array for the write operation, wherein the memory array is located on an external memory device; and

a second circuit that includes a plurality of output drivers to output write data to be written to the memory array during the write operation, wherein the write data is output after a number of clock cycles of an external clock signal transpire, wherein the write data is output in response to the control information, and wherein each output driver of the plurality of output drivers outputs two bits of the write data during a single clock cycle of the external clock signal.

2. The integrated circuit of claim 1, wherein:

the first circuit further receives, in a multiplexed format, control information that specifies a read operation, and address information specifying a location within the memory array for the read operation; and

the second circuit includes a plurality of input receivers to receive, after a predetermined number of clock cycles of the external clock signal transpire, read data corresponding to the read operation, wherein each input receiver of the plurality of input receivers receives two bits of the data during a single clock cycle of the external clock signal.

3. The integrated circuit of claim 2, wherein each input receiver of the plurality of input receivers includes a first input sampler and a second input sampler, wherein each of the first and second input samplers samples one bit of the two bits of data sampled by the input receiver during a single clock cycle of the external clock signal.

4. The integrated circuit of claim 2, wherein the second circuit includes output drivers to output a value, to the external memory device, that is representative of an amount of data to be written to the memory array of the external memory device.

5. The integrated circuit device of claim 1, wherein the second circuit includes output drivers to output a value, to the external memory device, that is representative of the number of clock cycles of the external clock signal.

6. The integrated circuit device of claim 1, wherein the plurality of output drivers of the second circuit includes output drivers to forward the address information to the external memory device.

7. The integrated circuit device of claim 1, wherein the plurality of output drivers output the control information and the address information to the external memory device in a multiplexed format.

8. The integrated circuit device of claim 1, wherein the first circuit receives the control information and the address information in a packet format, and wherein the first circuit includes a receiver to receive a signal that indicates the beginning of a packet that includes the control information and the address information.

9. The integrated circuit device of claim 1, further including a third circuit to generate a first internal clock signal, wherein each output driver of the plurality of output drivers outputs the data using the first internal clock signal, wherein the third circuit includes a feedback loop to control the timing relationship of the first internal clock signal with respect to the external clock signal.

10. The integrated circuit device of claim 9, wherein the third circuit further generates a second internal clock signal, wherein the first and second internal clock signals are complementary, and wherein the plurality of output drivers further outputs a first portion of the data using the first internal clock signal and the plurality of output drivers outputs a second portion of the data, in succession to the first portion of the data, using the second internal clock signal.

11. An integrated circuit device, comprising:

first receivers to receive address and control in a multiplexed format such that at least one receiver of the receivers receives a portion of both the address information and the control information, wherein the address information and the control information correspond to a read operation for a memory device;

output drivers to output an operation code and a read address, wherein the operation code and the read address are based on the address information and the control information; and

second receivers to receive read data, corresponding to the read operation, after a programmed number of clock cycles of an external clock signal, wherein each receiver of the second receivers receives two bits of the read data during a single clock cycle of the external clock signal.

12. The integrated circuit device of claim 11, wherein the programmed number of clock cycles is indicated by a value stored in a register, wherein the first receivers receive the value.

13. The integrated circuit of claim 11, wherein each receiver of the second receivers includes a first sampler and a second sampler, wherein each of the first and second samplers samples one bit of the two bits of the read data received during the single clock cycle of the external clock signal.

14. The integrated circuit device of claim 11, wherein the output drivers output the operation code and the address information to an external memory device, wherein the address information identifies a memory location within the external memory device.

15. The integrated circuit device of claim 11, wherein the output drivers output the operation code and the read address in a packet format, and wherein the output drivers include an output driver to output a signal that indicates the beginning of a packet that includes the operation code and the read address.

16. The integrated circuit device of claim 11, wherein the first receivers receives the control information and the address information in a packet format, and wherein the first receivers includes a receiver to receive a signal that indicates the beginning of a packet that includes the control information and the address information.

17. The integrated circuit device of claim 11, further including a circuit to generate a first internal clock signal, wherein the output drivers output the data using the first internal clock signal, wherein the circuit includes a feedback loop to control the timing relationship of the first internal clock signal with respect to the external clock signal.

18. The integrated circuit device of claim 17, wherein the circuit further generates a second internal clock signal, wherein the first and second internal clock signals are complementary, and wherein the output drivers further output a first portion of the data using the first internal clock signal and the output drivers output a second portion of the data, in succession to the first portion of the data, using the second internal clock signal.

19. The integrated circuit device of claim 11, wherein the first receivers receive the address information from a memory controller and the output drivers output the operation code and the read address to a memory device, wherein the memory device outputs the read data in response to the operation code.

20. The integrated circuit device of claim 11, where in each output driver of the output drivers outputs two consecutive bits of the address information during a single clock cycle of the external clock signal.

21. An integrated circuit comprising:

a first circuit to receive, in a multiplexed format, control information and address information, the control information specifying a write operation, and the address information specifying a location within a memory array for the write operation, wherein the memory array is located on an external memory device; and

a second circuit that includes a plurality of output drivers to output write data to be written to the memory array during the write operation, wherein the write data is output after a number of clock cycles of an external clock signal transpire, wherein the write data is output in response to the control information.

22. The integrated circuit of claim 21 wherein:

the first circuit further receives, in a multiplexed format, control information that specifies a read operation, and address information .specifying a location within the memory array for the read operation; and

the second circuit includes a plurality of input receivers to receive, after a predetermined number of clock cycles of the external clock signal transpire, read data corresponding to the read operation, wherein each input receiver of the plurality of input receivers receives two bits of the data during a single clock cycle of the external clock signal.

23. The integrated circuit of claim 22, wherein each input receiver of the plurality of input receivers includes a first input sampler and a second input sampler, wherein each of the first and second input samplers samples one bit of the two bits of data sampled by the input receiver during a single clock cycle of the external clock signal.

24. The integrated circuit of claim 22, wherein the second circuit includes output drivers to output a value that is representative of an amount of data to be written to the memory array of the external memory device.

25. The integrated circuit device of claim 21, wherein the second circuit includes output drivers to output a value to the external memory device, wherein the value is representative of the number of clock cycles of the external clock signal.

26. The integrated circuit device of claim 21, wherein the plurality of output drivers of the second circuit includes output drivers to forward the address information to the external memory device.

27. The integrated circuit device of claim 21, wherein the plurality of output drivers output the control information and the address information to the external memory device in a multiplexed format.

28. The integrated circuit device of claim 21, wherein the first circuit receives the control information and the address information in a packet format, and wherein the first circuit includes a receiver to receive a signal that indicates the beginning of a packet that includes the control information and the address information.

29. The integrated circuit device of claim 21, further including a third circuit to generate a first internal clock signal, wherein each output driver of the plurality of output drivers of the second circuit outputs the data using the first internal clock signal, wherein the third circuit includes a feedback loop to control the timing relationship of the first internal clock signal with respect to the external clock signal.

30. The integrated circuit device of claim 29, wherein the third circuit further generates a second internal clock signal, wherein the first and second internal clock signals are complementary, and wherein the plurality of output drivers further outputs a first portion of the data using the first internal clock signal and the plurality of output drivers outputs a second portion of the data, in succession to the first portion of the data, using the second internal clock signal.

31. A method of operation of an integrated circuit device, the method comprising:

receiving, in a multiplexed format, control information and address information, the control information specifying a write operation to an external memory device, and the address information specifying a location within a memory array of the memory device;

outputting an operation code that specifies the write operation; and

outputting data in response to the control information, after a predetermined number of clock cycles of an external clock signal transpire, wherein the data is to be written to the memory array during the write operation.

32. The method of claim 31, further including:

receiving control information specifying a read operation;

outputting an operation code that corresponds to the control information, wherein the memory device outputs read data in response to the operation code; and

sampling the read data, output by the first memory device, after a delay time transpires, wherein the sampling is done by input receivers on the integrated circuit device such that each input receiver samples two bits of the read data during a single clock cycle of the external clock signal.

33. The method of claim 31, further including outputting a value, to the memory device, that is representative of the predetermined number of clock cycles of the external clock signal.

34. The method of claim 31, further including:

receiving a value that is representative of the predetermined number of clock cycles of the external clock signal; and

outputting the value to the memory device.

35. The method of claim 31, further including outputting a value, to the memory device, that is representative of an amount of the data that the first memory device receives from the integrated circuit device.

36. The method of claim 31, wherein outputting data is done by output drivers on the integrated circuit device such that each output driver outputs two bits of the data for during a single clock cycle of the external clock signal.

37. The method of claim 31, further including forwarding the address information to the first memory device.

38. The method of claim 31, further including forwarding the control information to the first memory device.

39. The method of claim 31, further including:

generating a first internal clock signal using the external clock signal; and

controlling a timing relationship between the first internal clock signal and the external clock signal using a feedback loop;

wherein outputting data includes outputting data using the first internal clock signal.

40. The method of claim 39, further including generating a second internal clock signal, wherein the first and second internal clock signals are complementary, and wherein outputting data includes outputting the data using the second internal clock signal.

41. An integrated circuit device comprising:

means for receiving control information and address information in a multiplexed format, the control information specifying a write operation to an external memory device, and the address information specifying a memory location in the external memory device for the write operation; and

means for outputting data to the memory device after a predetermined number of clock cycles of an external clock signal transpire, wherein the data is to be written to the memory array during the write operation.