Integrated circuit device
First Claim
1. An integrated circuit comprising:
- a first circuit to receive, in a multiplexed format, control information and address information, the control information specifying a write operation, and the address information specifying a location within a memory array for the write operation, wherein the memory array is located on an external memory device; and
a second circuit that includes a plurality of output drivers to output write data to be written to the memory array during the write operation, wherein the write data is output after a number of clock cycles of an external clock signal transpire, wherein the write data is output in response to the control information, and wherein each output driver of the plurality of output drivers outputs two bits of the write data during a single clock cycle of the external clock signal.
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Abstract
An integrated circuit device is disclosed. In one particular exemplary embodiment, the integrated circuit device may comprise a first circuit to receive, in a multiplexed format, control information and address information, wherein the control information specifies a write operation and the address information specifies a location within a memory array for the write operation. The integrated circuit device may also comprise a second circuit that includes a plurality of output drivers to output write data to be written to the memory array during the write operation, wherein the write data is output after a number of clock cycles of an external clock signal transpire, wherein the write data is output in response to the control information, and wherein each output driver of the plurality of output drivers outputs two bits of the write data during a single clock cycle of the external clock signal.
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Citations
41 Claims
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1. An integrated circuit comprising:
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a first circuit to receive, in a multiplexed format, control information and address information, the control information specifying a write operation, and the address information specifying a location within a memory array for the write operation, wherein the memory array is located on an external memory device; and
a second circuit that includes a plurality of output drivers to output write data to be written to the memory array during the write operation, wherein the write data is output after a number of clock cycles of an external clock signal transpire, wherein the write data is output in response to the control information, and wherein each output driver of the plurality of output drivers outputs two bits of the write data during a single clock cycle of the external clock signal. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10)
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11. An integrated circuit device, comprising:
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first receivers to receive address and control in a multiplexed format such that at least one receiver of the receivers receives a portion of both the address information and the control information, wherein the address information and the control information correspond to a read operation for a memory device;
output drivers to output an operation code and a read address, wherein the operation code and the read address are based on the address information and the control information; and
second receivers to receive read data, corresponding to the read operation, after a programmed number of clock cycles of an external clock signal, wherein each receiver of the second receivers receives two bits of the read data during a single clock cycle of the external clock signal. - View Dependent Claims (12, 13, 14, 15, 16, 17, 18, 19, 20)
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21. An integrated circuit comprising:
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a first circuit to receive, in a multiplexed format, control information and address information, the control information specifying a write operation, and the address information specifying a location within a memory array for the write operation, wherein the memory array is located on an external memory device; and
a second circuit that includes a plurality of output drivers to output write data to be written to the memory array during the write operation, wherein the write data is output after a number of clock cycles of an external clock signal transpire, wherein the write data is output in response to the control information. - View Dependent Claims (22, 23, 24, 25, 26, 27, 28, 29, 30)
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31. A method of operation of an integrated circuit device, the method comprising:
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receiving, in a multiplexed format, control information and address information, the control information specifying a write operation to an external memory device, and the address information specifying a location within a memory array of the memory device;
outputting an operation code that specifies the write operation; and
outputting data in response to the control information, after a predetermined number of clock cycles of an external clock signal transpire, wherein the data is to be written to the memory array during the write operation. - View Dependent Claims (32, 33, 34, 35, 36, 37, 38, 39, 40)
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41. An integrated circuit device comprising:
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means for receiving control information and address information in a multiplexed format, the control information specifying a write operation to an external memory device, and the address information specifying a memory location in the external memory device for the write operation; and
means for outputting data to the memory device after a predetermined number of clock cycles of an external clock signal transpire, wherein the data is to be written to the memory array during the write operation.
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Specification