Overlay error model, sampling strategy and associated equipment for implementation

• US 6,975,974 B2
• Filed: 08/01/2001
• Issued: 12/13/2005
• Est. Priority Date: 02/26/2001
• Status: Active Grant

• Current Assignee: Macronix International Co., Ltd.
• Original Assignee: Macronix International Co., Ltd.
• Inventors: Chang, Kuo-Hao, Chen, Chih-Ping, Lin, Shun-Li, Chien, Chen-Fu
• Primary Examiner(s): FREJD, RUSSELL WARREN
• Application Number:
  US09/920,034
• Publication Number:
  US 20020183989A1
• Time in Patent Office: 1,595 Days
• Field of Search: 703/2, 700/109, 700118-121, 716 19- 21, 702/83, 702/150, 702/155, 250/548, 430/22, 355/53
• US Class Current: 703/2
• CPC Class Codes: G03F 7/705 Modelling or simulating from physical phenomena up to complete wafer processes or whole workflow in wafer productions
• CPC Class Codes: G03F 7/70533 Controlling abnormal operating mode, e.g. taking account of waiting time, decision to rework or rework flow
• CPC Class Codes: G03F 7/70633 Overlay, i.e. relative alignment between patterns printed by separate exposures in different layers, or in the same layer in multiple exposures or stitching
• CPC Class Codes: H01L 22/20 Sequence of activities consisting of a plurality of measurements, corrections, marking or sorting steps

Abstract

In the manufacturing of VLSI circuits, production of overlay is a critical step. To obtain a higher resolution and alignment accuracy in microlithographic process, overlay errors must be measured so that overlay errors can be reduced to a tolerable level. This invention provides an overlay error model and a sampling strategy. Utilizing the overlay model and sampling strategy, a device for measuring overlay errors is also designed.

Claims

1. A strategic sampling procedure for measuring overlay errors, including:

(a) determining a state within an intra-field, including determining the number and positions of selected overlays within the intra-field, determining each type of sampling state and sum of the selected overlays, ranking each type of intra-field overlay sampling state similarly on a wafer, and measuring locations and actual overlay error values of each overlay type of sampling states within the intra-field;

(b) using the measured values and utilizing a least square method to obtain coefficients according to overlay error model formulas (23) and (24), computing related square coefficient values between each type of overlay sampling states within the intra-field and the overlay model where R-square represents the degree of assessed variance explained by the model selecting a highest related square coefficient among the overlay sampling states within the intra-field so that model compensation is improved;

(c) determining a plurality of inter-field overlay sampling patterns, including determining locations and number of types of overlay sampling states within the inter-field, and together with the selected highest square coefficient from the overlay states within the intra-field in step (b), measuring locations and actual overlay error values of each overlay sampling pattern within the inter-field;

(d) using the measured values in step (c) and utilizing the least square method to find the coefficients in the model formulas (23) and (24), and computing related square coefficient values between each overlay sampling pattern within the inter-field and the overlay model, selecting an inter-field overlay sampling pattern having the highest related square coefficients, thereby finding an optimal sampling pattern that corresponds to the model and improving an effect of model compensation; and

(e) determining a combination of intra-field overlay sampling state and inter-field overlay sampling pattern and its relationship with the model so that the highest related coefficients are found, performing compensation and modification using the measured overlay errors for a stepper machine so that the number of overlay errors of exposed patterns is reduced and the yield of the semiconductor device is improved,

wherein the overlay error model uses formulas as follows;

d_x+X=T_x+X+E_XX−

(N+θ

)Y+M′

_xx−

R_yy+r_x+X 

 

(23)

d_y+Y=T_y+Y+E_yY−

(θ

−

N)X +M′

_yy+R_yx+r_y+Y 

 

(24)

with parameters in the model selected according to measured parameters and statistics, and setting $\begin{array}{c}N=\frac{R_x-R_y}{2}\\ \mathrm{\theta <br><br>}=\frac{R_x+R_y}{2}\end{array}$

where

N;

a non-positive crossing parameter;

θ

;

an angular rotation parameter;

x, y;

intra-field coordinates that use a central point of a selected region as an origin;

X, Y;

inter-field coordinates that use a central point of a wafer as an origin;

d_x+X, d_y+Y;

sum of intra-field overlay error and inter-field overlay error in horizontal and vertical directions, respectively;

T_x+X, T_y+Y;

sum of intra-field translation error and inter-field translation error in the horizontal and the vertical directions, respectively;

E_x+Y;

inter-field expansion error;

M′

_x, M′

_y;

magnification error in the horizontal and the vertical directions, respectively;

R_x, R_y;

intra-field rotation error in the horizontal and the vertical directions, respectively;

R_X, R_Y;

inter-field rotation error in the horizontal and the vertical directions, respectively; and

r_x+X, r_y+Y;

sum of intra-field residue and inter-field residue in the horizontal and the vertical directions, respectively.

2. The strategic sampling procedure of claim 1, wherein in step (a), total number of overlays in each sampling state is between 10 and 255.

3. The strategic sampling procedure of claim 2, wherein in step (b), the highest related square coefficient is the inter-field overlay sampling state (d).

4. The strategic sampling procedure of claim 3, wherein in step (c), the number of types of inter-field overlay sampling patterns in each region is between 2 and 51.

5. The strategic sampling procedure of claim 1, wherein the least square method includes a multiple linear regression analysis.