Method and computer software product for calculating and presenting a numerical value representative of a property of a circuit

• US 6,975,979 B2
• Filed: 07/06/1999
• Issued: 12/13/2005
• Est. Priority Date: 07/06/1998
• Status: Expired due to Fees

• Current Assignee: Renesas Electronics Corporation
• Original Assignee: NEC Corporation
• Inventors: Hirata, Morihisa, Akimoto, Tetsuya
• Primary Examiner(s): Homere, Jean R.
• Assistant Examiner(s): DAY, HERNG DER
• Application Number:
  US09/347,409
• Publication Number:
  US 20030158713A1
• Time in Patent Office: 2,352 Days
• Field of Search: 703/19, 703/13, 703/2, 702/117, 716/6
• US Class Current: 703/19
• CPC Class Codes: G06F 30/33 Design verification, e.g. functional simulation or model checking

Abstract

To calculate pin-to-pin delay time, which is delay time from the input pin to the output pin of a logic block, and block-to-block delay time, which is delay time from an output pin of one block to an input pin of the next block, firstly, the pin-to-pin delay time and the block-to-block delay time are calculated with negligence in aging caused by a hot carrier effect, secondly, degradations caused by aged transistors connected to the input pin and the output pin, and lastly, the pin-to-pin delay time and block-to-block delay time are modified by the degradation rate.

Claims

1. A method of calculating, by the use of a computer, pin-to-pin delay time T_iopath—

_aged, which is delay time of a signal passing between an input pin and an output pin of a logic block, and block-to-block delay time T<sub>connect—

aged</sub>, which is delay time of a signal passing between two said logic blocks connected to each other, comprising;

(a) calculating an amount of stress S_in cast by the input pin and an amount of stress S_out cast by the output pin according to the following expression;

$S={\mathrm{\alpha <br><br>}<br><br>\left(\frac{C}{W}\right)}^{\mathrm{\beta <br><br>}}$

where a load capacitance is represented by C[pF], constants depending on change of inputted waveform are represented by α and

β

, and width of channel of a transistor connected to a pin is represented by W[μ

m];

(b) calculating an aged delay time of the input pin δ

_in[%] and an aged delay time of the output pin δ

_out[%] according to the following expression;

$\mathrm{\delta <br><br>}={\mathrm{\gamma <br><br>}<br><br>\left(\frac{\mathrm{\tau <br><br>}<br><br><br><br>\mathrm{Sf}}{{\mathrm{\varepsilon <br><br>}}_1<br><br>{\mathrm{e<br><br>}}^{\mathrm{\kappa <br><br>}<br><br><br><br>T}}\right)}^{\frac{1}{{\mathrm{\varepsilon <br><br>}}_2}}$

where a constant depending on physical structure of the pin is represented γ

, the term of guarantee of a LSI is represented by τ

[hour], constants depending on process are represented by ε

1, ε

2 and κ

, working frequency is represented by f[Hz], and absolute temperature is represented by T[K];

(c) calculating and outputting for use as values representative of circuit properties of a logic level circuit the pin-to-pin delay time T<sub>iopath—

aged</sub> and the block-to-block delay time T<sub>connect—

aged</sub> according to the following expressions;

T<sub>iopath—

aged</sub>=T<sub>iopath—

fresh</sub>(1+λ

_inδ

_in+λ

_outδ

_out)

T<sub>connect—

aged</sub>=T<sub>connect—

fresh</sub>(1+λ

_outδ

_out)

where pin-to-pin delay time and block-to-block delay time calculated ignoring aging caused by hot carrier effect are represented by T<sub>iopath—

fresh</sub>[ps] and T<sub>connect—

fresh</sub>[ps], and ratios of delay times occurred at an input stage and an output stage to whole delay time occurred from the input pin to the output pin are represented by λ

_in and λ

_out.

2. A method of calculating, by the use of a computer, a delay time occurred to a signal passing through a logic level circuit that consists of a plurality of logic blocks, comprising:

(a) calculating pin-to-pin delay time T<sub>iopath—

aged</sub>, which is delay time of a signal passing between an input pin and an output pin of a bale block, and block-to-block delay time T<sub>connect—

aged</sub>, which is delay time of a signal passing between two said logic blocks connected to each other, comprising;

(i) calculating an amount of stress S_in cast by the input pin and an amount of stress S_out cast by the output pin according to the following expression;

$S={\mathrm{\alpha <br><br>}<br><br>\left(\frac{C}{W}\right)}^{\mathrm{\beta <br><br>}}$

where a load capacitance is represented by C[pF], constants depending on change of inputted waveform are represented by α and

β

, and width of channel of a transistor connected to a pin is represented by W[μ

m];

(ii) calculating an aged delay time of the input pin δ

_in[%] and an aped delay time of the output pin δ

_out[%] according to the following expression;

$\mathrm{\delta <br><br>}={\mathrm{\gamma <br><br>}<br><br>\left(\frac{\mathrm{\tau <br><br>}<br><br><br><br>\mathrm{Sf}}{{\mathrm{\varepsilon <br><br>}}_1<br><br>{\mathrm{e<br><br>}}^{\mathrm{\kappa <br><br>}<br><br><br><br>T}}\right)}^{\frac{1}{{\mathrm{\varepsilon <br><br>}}_2}}$

where a constant depending on physical structure of the pin is represented by γ

, the term of guarantee of a LSI is represented by τ

[hour], constants depending on process are represented by ε

1, ε

2 and κ

, working frequency is represented by f[Hz], and absolute temperature is represented by T[K];

(iii) calculating and outputting for use as values representative of circuit properties of the logic level circuit the pin-to-pin delay time T<sub>iopath—

aged</sub> and the block-to-block delay time T<sub>connect—

aged</sub> according to the following expressions;

T<sub>iopath—

aged</sub>=T<sub>iopath—

fresh</sub>(1+λ

_inδ

_in+λ

_outδ

_out)

T<sub>connect—

aged</sub>=T<sub>connect—

fresh</sub>(1+λ

_outδ

_out)

where pin-to-pin delay time and block-to-block delay time calculated ignoring aging caused by hot carrier effect are represented by and T<sub>iopath—

fresh</sub>[ps] and T<sub>connect—

fresh</sub>[ps], and ratios of delay times occurred at an input stage and an output stage to whole delay time occurred from the input pin to the output pin are represented by λ

_in, and λ

_out; and

(b) calculating and outputting for use as a value representative of a circuit property of said logic level circuit the delay time of the logic level circuit from the result of step (a).

3. A computer-readable medium incorporating a program of instructions for calculating, by using a computer, pin-to-pin delay time T_iopath—

_aged, which is delay time of a signal passing between an input pin and an output pin of a logic block, and block-to-block delay time T<sub>connect—

aged</sub>, which is delay time of a signal passing between two said logic blocks connected to each other, the program making a computer execute the following processes;

(a) calculating an amount of stress S_in cast by the input pin and an amount of stress S_out cast by the output pin according to the following expression;

$S={\mathrm{\alpha <br><br>}<br><br>\left(\frac{C}{W}\right)}^{\mathrm{\beta <br><br>}}$

where a load capacitance is represented by C[pF], constants depending on change of inputted waveform are represented by α and

β

, and width of channel of a transistor connected to a pin is represented by W[μ

m];

(b) calculating an aged delay time of the input pin δ

_in[%] and an aged delay time of the output pin δ

_out[%] according to the following expression;

$\mathrm{\delta <br><br>}={\mathrm{\gamma <br><br>}<br><br>\left(\frac{\mathrm{\tau <br><br>}<br><br><br><br>\mathrm{Sf}}{{\mathrm{\varepsilon <br><br>}}_1<br><br>{\mathrm{e<br><br>}}^{\mathrm{\kappa <br><br>}<br><br><br><br>T}}\right)}^{\frac{1}{{\mathrm{\varepsilon <br><br>}}_2}}$

where that a constant depending on physical structure of the pin is represented by γ

, the term of a guarantee of a LSI is represented by τ

[hour], constants depending on process are represented by ε

1, ε

2 and κ

, working frequency is represented by f[Hz], and absolute temperature is represented by T[K];

(c) calculating and outputting for use as values representative of circuit properties of a logic level circuit the pin-to-pin delay time T<sub>iopath—

aged</sub> and the block-to-block delay time T<sub>connect—

aged</sub> according to the following expressions;

T<sub>iopath—

aged</sub>=T<sub>iopath—

fresh</sub>(1+λ

_inδ

_in+λ

_outδ

_out)

T<sub>connect—

aged</sub>=T<sub>connect—

fresh</sub>(1+λ

_outδ

_out)

where pin-to-pin delay time and block-to-block delay time calculated ignoring aging caused by hot carrier effect are represented by T<sub>iopath—

fresh</sub>[ps] and T<sub>connect—

fresh</sub>[ps], and ratios of delay times occurred at an input stage and an output stage to whole delay time occurred from the input pin to the output pin are represented by λ

_in and λ

_out, respectively.

4. A computer-readable medium incorporating a program of instructions for calculating a delay time occurred to a signal passing through a logic level circuit that consists of a plurality of logic blocks, the program making a computer execute the following processes:

(a) calculating pin-to-pin delay time T<sub>iopath—

aged</sub>, which is delay time of a signal passing between an input pin and an output pin of a logic block, and block-to-block delay time T<sub>connect—

aged</sub>, which is delay time of a signal passing between two said logic blocks connected to each other, said calculating comprises;

(i) calculating an amount of stress S_in cast by the input pin and an amount of stress S_out cast by the output pin according to the following expression;

$S={\mathrm{\alpha <br><br>}<br><br>\left(\frac{C}{W}\right)}^{\mathrm{\beta <br><br>}}$

where a load capacitance is represented by C[pF], constants depending on change of inputted waveform are represented by α and

β

, and width of channel of a transistor connected to a pin is represented by W[μ

m];

(ii) calculating an aged delay time of the input pin δ

_in[%] and an aged delay time of the output pin δ

_out[%] according to the following expression;

$\mathrm{\delta <br><br>}={\mathrm{\gamma <br><br>}<br><br>\left(\frac{\mathrm{\tau <br><br>}<br><br><br><br>\mathrm{Sf}}{{\mathrm{\varepsilon <br><br>}}_1<br><br>{\mathrm{e<br><br>}}^{\mathrm{\kappa <br><br>}<br><br><br><br>T}}\right)}^{\frac{1}{{\mathrm{\varepsilon <br><br>}}_2}}$

where that a constant depending on physical structure of the pin is represented by γ

, the term of a guarantee of a LSI is represented by τ

[hour], constants depending on process are represented by ε

1, ε

2 and κ

, working frequency is represented by f[Hz], and absolute temperature is represented by T[K];

(iii) calculating and outputting for use as values representative of circuit properties of said logic level circuit the pin-to-pin delay time T<sub>iopath—

aged</sub> and the block-to-block delay time T<sub>connect—

aged</sub> according to the following expressions;

T<sub>iopath—

aged</sub>=T<sub>iopath—

fresh</sub>(1+λ

_inδ

_in+λ

_outδ

_out)

T<sub>connect—

aged</sub>=T<sub>connect—

fresh</sub>(1+λ

_outδ

_out)

where pin-to-pin delay time and block-to-block delay time calculated ignoring aging caused by hot carrier effect are represented by T<sub>iopath—

fresh</sub>[ps] and T<sub>connect—

fresh</sub>[ps], and ratios of delay times occurred at an input stage and an output stage to whole delay time occurred from the input pin to the output pin are represented by λ

_in and λ

_out, respectively; and

(b) calculating and outputting for use as a value representative of a circuit property of said logic level circuit the delay time of the logic level circuit from to result of step (a).