Hierarchical linking module connection to access ports of embedded cores

• US 6,975,980 B2
• Filed: 06/14/2002
• Issued: 12/13/2005
• Est. Priority Date: 02/18/1998
• Status: Expired due to Term

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: Whetsel, Lee D.
• Primary Examiner(s): Teska, Kevin J.
• Assistant Examiner(s): Ferris, III, Fred O
• Application Number:
  US10/172,568
• Publication Number:
  US 20020162063A1
• Time in Patent Office: 1,278 Days
• Field of Search: 703/23, 703/25, 714/724, 714/726, 714/727
• US Class Current: 703/25
• CPC Class Codes: G01R 31/3177 Testing of logic operation, e.g. by logic analysers
• CPC Class Codes: G01R 31/318555 Control logic
• CPC Class Codes: G01R 31/318558 Addressing or selecting of subparts of the device under test
• CPC Class Codes: G01R 31/318561 Identification of the subpart
• CPC Class Codes: G01R 31/318563 Multiple simultaneous testing of subparts
• CPC Class Codes: G01R 31/318572 Input/Output interfaces

Abstract

An integrated circuit can have plural core circuits, each having a test access port that is defined in IEEE Standard 1149.1. Access to and control of these ports is though a test linking module. The test access ports on an integrated circuit can be arranged in a hierarchy with one test linking module controlling access to plural secondary test linking modules and test access ports. Each secondary test linking module in turn can also control access to tertiary test linking modules and test access ports. The test linking modules can also be used for emulation.

Claims

1. An integrated circuit comprising:

A. emulation interface pads;

B. a first linking module connected to the emulation interface pads, including an enable input lead connected between the first linking module and the emulation input pads;

C. first core circuits including first functional circuits, first boundary scan registers connected to the functional circuits, and a first access port connected to the first boundary scan registers, the first access port being connected to the emulation pads, having a first select output lead connected to the emulation interface pads, and being connected to the first linking module;

D. a second linking module connected to the emulation interface pads and to the first linking module; and

E. second core circuits including second functional circuits, second boundary scan registers connected to the second functional circuits, and a second access port connected to the second boundary scan registers, the second access port being connected to the emulation interface pads and the second linking module.

2. The integrated circuit of claim 1 in which the first linking module includes a second select input lead and a first enable output lead, and in which the first access port includes a second select output lead connected to the second select input lead of the first linking module and an enable input lead connected to the first enable output lead of the linking module.

3. The integrated circuit of claim 1 in which the first linking module includes a second select input lead and a first enable output lead, and in which the first access port includes a second select output lead connected to the second select input lead of the first linking module and an enable input lead connected to the first enable output lead of the linking module, the first linking module further including a gate having a first input connected to the enable input lead, a second input connected to an update register, and an output connected to the first enable output lead.

4. The integrated circuit of claim 1 in which the second access port has two select output leads, of which one is connected to the second linking module, and a second enable input lead connected to the second linking module.

5. The integrated circuit of claim 1 including:

i. a third linking module connected to the emulation interface pads and to the second linking module; and

ii. third core circuits including third functional circuits, third boundary scan registers connected to the third functional circuits, and a third access port connected to the third boundary scan registers, the third access port being connected to the emulation interface pads and the third linking module.

6. The integrated circuit of claim 1 including:

i. a third linking module connected to the emulation interface pads and to the second linking module; and

ii. third core circuits including third functional circuits, third boundary scan registers connected to the third functional circuits, and a third access port connected to the third boundary scan registers, the third access port being connected to the emulation interface pads and the third linking module, the third access port has two select output leads, of which one is connected to the third linking module, and a third enable input lead connected to the third linking module.