Circuit and method for correcting erroneous data in memory for pipelined reads

• US 6,976,204 B1
• Filed: 06/15/2001
• Issued: 12/13/2005
• Est. Priority Date: 06/15/2001
• Status: Active Grant

• Current Assignee: Advanced Micro Devices, Inc.
• Original Assignee: Advanced Micro Devices, Inc.
• Inventors: Mudgett, Dan S., Chambers, Eric G., Magro, James R.
• Primary Examiner(s): Decady, Albert
• Assistant Examiner(s): ABRAHAM, ESAW T
• Application Number:
  US09/882,417
• Time in Patent Office: 1,642 Days
• Field of Search: 714/763, 714/758, 714/764, 714/48
• US Class Current: 714/763
• CPC Class Codes: G06F 11/106 Correcting systematically all correctable errors, i.e. scrubbing
• CPC Class Codes: G11C 7/1006 Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor
• CPC Class Codes: G11C 7/1039 using pipelining techniques, i.e. using latches between functional memory parts, e.g. row/column decoders, I/O buffers, sense amplifiers

Abstract

A circuit and method for correcting erroneous data in memory for pipelined reads. A memory controller includes a control unit, a storage unit and an error detection and correction unit. The control unit is configured to read data including an associated error correction code from a memory subsystem in response to a memory read request. The error detection and correction unit is coupled to receive the data and configured to determine whether an error exists in that data based upon the associated error correction code. The control unit is configured to store an indication in the storage unit that the data corresponding to the memory read request is erroneous. The control unit is further configured to detect the indication in the storage unit and to responsively perform a subsequent read of the data from the memory subsystem and to write a corrected version of the data back to the memory subsystem.

Claims

1. A memory controller comprising:

a control unit configured to read data including an associated error correction code from a memory subsystem in response to a memory read request;

a storage unit coupled to said control unit;

an error detection and correction unit coupled to receive said data and configured to determine whether an error exists in said data based upon said associated error correction code;

wherein said control unit is configured to store an indication in said storage unit that said data corresponding to said memory read request is erroneous; and

wherein said control unit is further configured to subsequently detect said indication in said storage unit and to responsively perform a subsequent read of said data from said memory subsystem and to write a corrected version of said data within said memory subsystem.

2. The memory controller as recited in claim 1, wherein said error detection and correction unit is further configured to provide said corrected version of said data in response to said subsequent read of said data.

3. The memory controller as recited in claim 1, wherein said indication includes an address in said memory subsystem of said data corresponding to said read request.

4. The memory controller as recited in claim 1, wherein said control unit is further configured to inhibit accepting an additional memory read request in response to said indication.

5. The memory controller as recited in claim 4, wherein said control unit is further configured to accept said additional memory read request in response to said subsequent read of said data from said memory subsystem and a corrected version of said data being written to said memory subsystem.

6. A data processing system comprising:

a processor;

a memory subsystem configured to store data;

a system controller including a memory controller coupled between said processor and said memory subsystem, wherein said memory controller includes;

a control unit configured to read data including an associated error correction code from a memory subsystem in response to a memory read request;

a storage unit coupled to said control unit;

an error detection and correction unit coupled to receive said data and configured to determine whether an error exists in said data based upon said associated error correction code;

wherein said control unit is configured to store an indication in said storage unit that said data corresponding to said memory read request is erroneous; and

wherein said control unit is further configured to subsequently detect said indication in said storage unit and to responsively perform a subsequent read of said data from said memory subsystem and to write a corrected version of said data within said memory subsystem.

7. The data processing system as recited in claim 6, wherein said error detection and correction unit is further configured to provide said corrected version of said data in response to said subsequent read of said data.

8. The data processing system as recited in claim 6, wherein said indication includes an address in said memory subsystem of said data corresponding to said read request.

9. The data processing system as recited in claim 6, wherein said control unit is further configured to inhibit accepting an additional memory read request in response to said indication.

10. The data processing system as recited in claim 9, wherein said control unit is further configured to accept said additional memory read request in response to said subsequent read of said data from said memory subsystem and a corrected version of said data being written to said memory subsystem.

11. A method of correcting erroneous data in a memory of a memory subsystem, said method comprising:

reading data including an associated error correction code from said memory subsystem in response to a memory read request;

receiving said data and determining whether an error exists in said data based upon said associated error correction code;

storing an indication that said data corresponding to said memory read request is erroneous; and

subsequently detecting said indication and responsively performing a subsequent read of said data from said memory subsystem and writing a corrected version of said data within said memory subsystem.

12. The method as recited in claim 11 further comprising providing said corrected version of said data in response to said subsequent read of said data.

13. The method as recited in claim 11, wherein said indication includes an address in said memory subsystem of said erroneous data corresponding to said read request.

14. The method as recited in claim 11 further comprising inhibiting accepting an additional memory read request in response to said indication.

15. The method as recited in claim 14 further comprising accepting said additional memory read request in response to performing said subsequent read of said data from said memory subsystem and to said writing of said corrected version of said data to said memory subsystem.