Method and apparatus for calculating TCP and UDP checksums while preserving CPU resources

• US 6,976,205 B1
• Filed: 09/21/2001
• Issued: 12/13/2005
• Est. Priority Date: 09/21/2001
• Status: Active Grant

• Current Assignee: Rambus Inc.
• Original Assignee: Syrus Ziai
• Inventors: Ziai, Syrus, Jordan, Paul, Robson, Craig, Donohue, Ryan, Pong, Fong
• Primary Examiner(s): Baker, Stephen M.
• Application Number:
  US09/962,724
• Time in Patent Office: 1,544 Days
• Field of Search: 714/807
• US Class Current: 714/807
• CPC Class Codes: H04L 1/0061 Error detection codes
• CPC Class Codes: H04L 69/12 Protocol engines
• CPC Class Codes: H04L 69/16 Implementation or adaptation of Internet protocol [IP], of transmission control protocol [TCP] or of user datagram protocol [UDP]
• CPC Class Codes: H04L 69/163 In-band adaptation of TCP data exchange; In-band control procedures
• CPC Class Codes: H04L 69/164 Adaptation or special uses of UDP protocol
• CPC Class Codes: H04L 69/326 in the transport layer [OSI layer 4] H04L69/16 takes precedence

Abstract

A method is described that involves performing a checksum calculation on a section of data within an inbound packet before the section of data is first stored into a system memory. Another method is described that involves moving a section of data within an outbound packet from a system memory to an offload memory. Then, removing the section of data from the offload memory; and performing a checksum calculation on the section of data. An apparatus is described that includes a central processing unit that is communicatively coupled with a network processing offload unit, wherein the network processing offload unit calculates a checksum upon a section of data located within an inbound packet, and calculates a checksum upon a section of data within an outbound packet.

Claims

1. A network offload acceleration unit, comprising:

a. a first checksum engine to calculate a first checksum over a first block of data, said first block of data part of a first outbound packet;

b. a second checksum engine to calculate a second checksum over a second block of data, said second block of data part of a second outbound packet;

c. a third checksum engine to calculate a third checksum over a third block of data, said third block of data part of an inbound packet wherein said third checksum engine further comprises a queue to receive said third block of data and checksum processing logic circuitry to perform said calculation of said third checksum; and

,

d. a bus coupled to said first outbound checksum engine, said second outbound checksum engine and said inbound checksum engine.

2. The network offload acceleration unit as in claim 1 wherein said first outbound packet comprises a UDP packet, said second outbound packet comprises a TCP packet, and said inbound packet comprises a packet structure selected from the group consisting of:

a) a UDP packet; and

,

b) a TCP packet.

3. The network offload acceleration unit as in claim 1 wherein said first checksum engine has an output that is communicatively coupled to a network interface.

4. The network offload acceleration unit as in claim 1 wherein said third checksum engine has an input that is communicatively coupled to a network interface.

5. The network offload acceleration unit of claim 1 further comprising an offload memory coupled to said bus.

6. The network offload acceleration unit of claim 1 wherein said network processing offload unit is communicatively coupled to a CPU.

7. The network offload acceleration unit of claim 1 wherein said first checksum engine further comprises a queue to receive said first block of data and checksum processing logic circuitry to perform said calculation of said first checksum.

8. The network offload acceleration unit of claim 7 further comprising a register coupled to said checksum processing logic circuitry.

9. The network offload acceleration unit of claim 8 wherein said register is coupled to said bus.

10. The network offload acceleration unit of claim 7 wherein said second checksum engine further comprises a queue to receive pieces of said second block of data on a piece by piece basis and checksum processing logic circuitry to performs said calculation of said second.

11. The network offload acceleration unit of claim 10 further comprising a register coupled to said checksum processing logic circuitry.

12. An apparatus, comprising:

a. a first checksum engine comprising first logic circuitry to calculate a first checksum over a first block of data, said first block of data part of a first outbound packet;

b. a second checksum engine comprising second logic circuitry to calculate a second checksum over a second block of data, said second block of data part of a second outbound packet wherein said first checksum engine further comprises a queue to store said first block of data and said second checksum engine comprises a queue that can only store a piece of said second block of data as opposed to the entirety of said second block of data, said first outbound packet comprising a TCP packet, said second outbound packet comprising a UDP packet;

c. a third checksum engine comprising third logic circuitry to calculate a third checksum over a third block of data, said third block of data part of an inbound packet; and

,

d. a bus coupled to said first outbound checksum engine, said second outbound checksum engine and said inbound checksum engine.

13. The method of claim 12 wherein said third checksum engine is coupled to a network interface and said bus is communicatively coupled to CPU through a memory controller.

14. The apparatus of claim 12 further comprising a memory controller coupled to said bus.

15. The apparatus of claim 14 further comprising a memory coupled to said memory controller.

16. The apparatus of claim 15 further comprising a CPU coupled to said bus.

17. The apparatus of claim 16 wherein said CPU is coupled to said bus through a second memory controller.

18. The apparatus of claim 17 further comprising a second memory coupled to said second memory controller.

19. The apparatus of claim 18 wherein said CPU is coupled to said bus through said second memory controller and a bridge.