Structure and method to improve channel mobility by gate electrode stress modification

• US 6,977,194 B2
• Filed: 10/30/2003
• Issued: 12/20/2005
• Est. Priority Date: 10/30/2003
• Status: Active Grant

• Current Assignee: Globalfoundries US Incorporated (GlobalFoundries, Inc.)
• Original Assignee: International Business Machines Corporation
• Inventors: Chidambarrao, Dureseti, Doris, Bruce B., Belyansky, Michael P., Dokumaci, Omer H., Gluschenkov, Oleg
• Primary Examiner(s): WOJCIECHOWICZ, EDWARD JOSEPH
• Application Number:
  US10/695,752
• Publication Number:
  US 20050093059A1
• Time in Patent Office: 782 Days
• Field of Search: 257/257, 257/369, 257/370, 438/197
• US Class Current: 438/197
• CPC Class Codes: H01L 21/823807 with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
• CPC Class Codes: H01L 21/823835 silicided or salicided gate conductors
• CPC Class Codes: H01L 21/823842 gate conductors with different gate conductor materials or different gate conductor implants, e.g. dual gate structures
• CPC Class Codes: H01L 29/4908 for thin film semiconductor, e.g. gate of TFT
• CPC Class Codes: H01L 29/66795 with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/7845 the means being a conductive material, e.g. silicided S/D or Gate
• CPC Class Codes: H01L 29/785 having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET

Abstract

In producing complementary sets of metal-oxide-semiconductor (CMOS) field effect transistors, including nFET and pFET), carrier mobility is enhanced or otherwise regulated through the reacting the material of the gate electrode with a metal to produce a stressed alloy (preferably CoSi₂, NiSi, or PdSi) within a transistor gate. In the case of both the nFET and pFET, the inherent stress of the respective alloy results in an opposite stress on the channel of respective transistor. By maintaining opposite stresses in the nFET and pFET alloys or silicides, both types of transistors on a single chip or substrate can achieve an enhanced carrier mobility, thereby improving the performance of CMOS devices and integrated circuits.

Claims

1. A method of adjusting carrier mobility in semiconductor devices comprising the steps of

depositing a metal or combination of metals to contact one of a first or second transistor gate structure, wherein said depositing step comprises

depositing a first metal or combination of metals to a portion of gate electrode material in said first or second transistor structure to form an alloy at the lower region of the gate electrode proximate to the channel of said first or second transistor;

and

depositing a second metal or combination of metals over said first or second transistor gate electrode to form a first stressed alloy within said first or second transistor gate in the upper region of the gate electrode, and

alloying said metal or combination of metals and said one of a first and second transistor gate structure to form at least said first stressed alloy within said one of a first or second transistor gate whereby a first stress is created in at least one corresponding channel of first or second transistors without producing a stress in a channel of the other transistor of said first or second transistors.

2. A method as recited in claim 1 wherein said depositing step further comprises

depositing a metal or combination of metals to a portion of said gate electrode material in said other transistor of said first and second transistors to form an alloy at the lower region of the gate electrode proximate to the channel of said other transistor;

and

depositing a metal or combination of metals over said other transistor gate electrode to form a stressed alloy within said other transistor gate in the upper region of the gate electrode, and

alloying said metal or combination of metals and said transistor gate structure to form at least a second stressed alloy within said transistor gate of said other transistor, whereby said second stressed alloy within said other transistor gate electrode creates a second stress in a channel area of said other transistor.

3. A method as recited in claim 2 wherein the first stressed alloy and second stressed alloy are of opposing stresses.

4. A method as recited in claim 3 wherein the first transistor and second transistor are of opposite conductivity types.

5. A method as recited in claim 4 wherein

said first transistor is an nFET wherein said first stressed alloy is compressive creating said first stress wherein first stress is tensile, and

said second transistor is a pEET wherein said second stressed alloy is tensile creating said second stress wherein second stress is compressive.