Output regulator

• US 6,977,492 B2
• Filed: 06/12/2003
• Issued: 12/20/2005
• Est. Priority Date: 07/10/2002
• Status: Active Grant

• Current Assignee: Marvell Asia Pte Limited (Marvell Technology Group Limited)
• Original Assignee: Marvell World Trade Limited (Marvell Technology Group Limited)
• Inventors: Zhang, Jiancheng, Sutardja, Sehat, He, Runsheng
• Primary Examiner(s): NGUYEN, MATTHEW VAN
• Application Number:
  US10/460,825
• Publication Number:
  US 20040008016A1
• Time in Patent Office: 922 Days
• Field of Search: 323/234, 323/266, 323/268, 323/271, 323273-279, 323281-285
• US Class Current: 323/283
• CPC Class Codes: H02M 1/0009 Devices or circuits for detecting current in a converter
• CPC Class Codes: H02M 1/0012 Control circuits using digital or numerical techniques in DC/DC converters H02M3/157, H02M3/33515; in DC-AC converters H02M7/53873
• CPC Class Codes: H02M 1/0025 Arrangements for modifying reference values, feedback values or error values in the control loop of a converter
• CPC Class Codes: H02M 1/0048 Circuits or arrangements for reducing losses using snubbers H02M1/34
• CPC Class Codes: H02M 1/088 for the simultaneous control of series or parallel connected semiconductor devices
• CPC Class Codes: H02M 1/38 Means for preventing simultaneous conduction of switches
• CPC Class Codes: H02M 3/157 with digital control
• CPC Class Codes: H02M 3/158 including plural semiconductor devices as final control devices for a single load
• CPC Class Codes: H02M 3/1588 comprising at least one synchronous rectifier element H02M3/1582, H02M3/1584 take precedence
• CPC Class Codes: H03K 17/122 in field-effect transistor switches
• CPC Class Codes: H03K 17/167 using parallel switching arrangements
• CPC Class Codes: H03K 17/6871 the output circuit comprising more than one controlled field-effect transistor
• CPC Class Codes: H03K 5/1565 the output pulses having a constant duty cycle
• CPC Class Codes: Y02B 70/10 Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes

Abstract

A control system for controlling an output regulator having a regulated output. The control system including an output sensor to generate a digital sense signal to indicate within which of at least three reference ranges the regulated output is included. Each of the at least three reference ranges including a plurality of possible values of the regulated output. A digital controller, responsive to the digital sense signal, to generate a drive signal to control the regulated output.

Claims

1. A control system for controlling an output regulator having a regulated output, comprising:

an output sensor to generate a digital sense signal to indicate within which of at least three reference ranges the regulated output is included, each of the at least three reference ranges including a plurality of possible values of the regulated output; and

a digital controller, responsive to the digital sense signal, to generate a drive signal to control the regulated output.

2. The control system of claim 1 wherein the reference ranges are selected from the group consisting of overlapping and consecutive.

3. The control system of claim 1 wherein the digital sense signal represents a difference between a reference voltage and the regulated output.

4. The control system of claim 1 wherein the digital controller further comprises a control mode selected from the group consisting of voltage mode and current mode.

5. The control system of claim 1 further comprising a power stage, wherein the digital controller further generates a duty cycle estimation for controlling the power stage.

6. The control system of claim 5 wherein the digital controller further comprises a delay line to adjust the duty cycle estimation, the delay line to receive an input pulse signal corresponding to the duty cycle estimation and a select signal.

7. The control system of claim 6 wherein the delay line includes an interpolator.

8. The control system of claim 6 wherein the delay includes:

a plurality of delay circuits to generate delay signals referenced to the input pulse signal, at least one of the delay circuits in communication with the input pulse signal, each of the delay circuits having a delay time;

a select module, in response to the select signal, to select at least one of the delay signals; and

a combiner to combine the input pulse signal and the selected delay signal to generate the output pulse width signal, the output pulse width signal to set a pulse width for the output regulator.

9. The control system of claim 8 wherein a relationship of the delay time of each of the plurality of delay circuits is selected from a group consisting of approximately equal, binary, and exponential.

10. The control system of claim 8 wherein the selected delay signal has a time delay approximately equal to a pulse width error.

11. The control system of claim 5 further including a duty cycle generator to generate the drive signal as a function of the duty cycle estimation, the duty cycle generator including:

a counter, responsive to a clock signal having a clock period, to generate the drive signal having a pulse width, the pulse width being approximately an integer multiple of the clock period; and

the counter including a counter limit input to receive a digital duty cycle signal corresponding to the duty cycle estimation, the digital duty cycle signal to set a quantity of clock periods to count such that the pulse width is approximately equal to the clock period multiplied by the digital duty cycle signal.

12. The control system of claim 11 further comprising a delay line to finetune the pulse width of the drive signal.

13. The control system of claim 11 further comprising a control block to generate a delay control signal in response to the drive signal and the digital duty cycle signal, the delay control signal to represent a quantization error of the pulse width.

14. The control system of claim 1 wherein the regulated output is selected from the group comprising output voltage and output current.

15. The control system of claim 1 further comprising an output selector to set a nominal value of the regulated output.

16. The control system of claim 15 wherein the output selector generates a reference signal in response to an input, the reference signal to set the nominal value of the regulated output.

17. The control system of claim 1 further including a storage system for capturing state information of the output regulator, the storage system comprising:

an information controller in communication with the output regulator to capture the state information, the state information being in a digital format; and

a memory in communication with the information controller to store the state information.

18. The control system of claim 17 further comprising a state information analyzer to analyze the stored information.

19. The control system of claim 17 wherein the state information is selected from a group consisting of output voltage, output current, nominal duty cycle, adjusted duty cycle, power switch on-time, power switch off-time, and adjustment value.

20. The control system of claim 17 wherein the output regulator has a switching frequency;

and

the information controller captures the state information at a rate greater than the switching frequency of the output regulator.

58. The control system of claim 1 wherein the drive signal controls the regulated output such that each of the at least three reference ranges results in a corresponding operating mode.

61. The control system of claim 1 wherein each of the at least three reference ranges has an upper limit and a lower limit, wherein a difference between the upper and lower limits of at least one of the at least three reference ranges is different than a difference between upper and lower limits of remaining ones of the at least three reference ranges.

21. A method of controlling an output regulator having a regulated output, comprising:

generating a digital sense signal to indicate within which of at least three reference ranges the regulated output is included, each of the at least three reference ranges including a plurality of possible values of the regulated output; and

generating a drive signal, in response to the digital sense signal, to control the regulated output.

22. The method of claim 21 wherein the reference ranges are selected from the group consisting of overlapping and consecutive.

23. The method of claim 21 wherein generating the digital sense signal includes determining a difference between a reference voltage and the regulated output.

24. The method of claim 21 further comprising a control mode selected from the group consisting of voltage mode and current mode.

25. The method of claim 21 wherein generating the drive signal further includes generating a duty cycle estimation for controlling the generating of a power output.

26. The method of claim 25 wherein generating the duty cycle estimation further includes generating an incremental delay to adjust the duty cycle estimation.

27. The method of claim 26 wherein generating the incremental delay includes;

receiving an input pulse signal corresponding to the duty cycle estimation;

generating a plurality of delay signals referenced to the input pulse signal, each of the delay signals having a delay time;

selecting at least one of the delay signals;

combining the input pulse signal and the selected delay signal; and

generating the output pulse width signal based on the combining, the output pulse width signal to set a pulse width for the output regulator.

28. The method of claim 27 wherein a relationship of the delay time of each of the plurality of delay signals is selected from a group consisting of approximately equal, binary, and exponential.

29. The method of claim 27 wherein the selecting includes selecting one of the delay signals having a delay time approximately equal to a pulse width error.

30. The method of claim 25 wherein generating the drive signal further includes receiving a digital duty cycle signal corresponding to the duty cycle estimation;

setting a counter limit to approximately the duty cycle estimation;

counting a quantity of clock pulses approximately equal to the counter limit, the clock pulses having a clock period; and

setting a pulse width of the drive signal to approximately the quantity of clock pulses multiplied by the clock period.

31. The method of claim 30 further comprising applying an incremental delay to the drive signal to finetune the pulse width.

32. The method of claim 30 further comprising generating a delay control signal as a function of the drive signal and the digital duty cycle signal, the delay control signal to represent a quantization error of the pulse width.

33. The method of claim 21 wherein the regulated output is selected from the group comprising output voltage and output current.

34. The method of claim 21 further comprising setting a nominal value of the regulated output.

35. The method of claim 34 wherein setting the nominal value further includes generating a reference signal in response to an input, the reference signal to set the nominal value of the regulated output.

36. The method of claim 21 further comprising storing state information of the output regulator;

and

analyzing the stored state information.

37. The method of claim 36 wherein the state information is selected from a group consisting of output voltage, output current, nominal duty cycle, adjusted duty cycle, power switch on-time, power switch off-time, and adjustment value.

38. The method of claim 36 wherein the output regulator has a switching frequency;

and

further includes capturing the state information at a rate greater than the switching frequency of the output regulator.

59. The method of claim 21 wherein the drive signal controls the regulated output such that each of the at least three reference ranges results in a corresponding operating mode.

62. The method of claim 21 wherein each of the at least three reference ranges has an upper limit and a lower limit, wherein a difference between the upper and lower limits of at least one of the at least three reference ranges is different than a difference between upper and lower limits of remaining ones of the at least three reference ranges.

39. A control system for controlling an output regulator having a regulated output, comprising:

means for generating a digital sense signal to indicate within which of at least three reference ranges the regulated output is included, each of the at least three reference ranges including a plurality of possible values of the regulated output; and

means for generating a drive signal, in response to the digital sense signal, to control the regulated output.

40. The control system of claim 39 wherein the reference ranges are selected from the group consisting of overlapping and consecutive.

41. The control system of claim 39 wherein the means for generating the digital sense signal includes means for determining a difference between a reference voltage and the regulated output.

42. The control system of claim 39 further comprising a control mode selected from the group consisting of voltage mode and current mode.

43. The control system of claim 39 further comprising means for generating a power output, wherein the means for generating the drive signal further includes means for generating a duty cycle estimation for controlling the means for generating the power output.

44. The control system of claim 43 wherein the means for generating the duty cycle estimation further includes means for generating an incremental delay to adjust the duty cycle estimation.

48. The control system of claim 43 wherein the means for generating the drive signal further includes means for receiving a digital duty cycle signal corresponding to the duty cycle estimation;

means for setting a counter limit to approximately the duty cycle estimation;

means for counting a quantity of clock pulses approximately equal to the counter limit, the clock pulses having a clock period; and

means for setting a pulse width of the drive signal to approximately the quantity of clock pulses multiplied by the clock period.

49. The control system of claim 48 further comprising means for applying an incremental delay to the drive signal to finetune the pulse width.

50. The control system of claim 48 further comprising means for generating a delay control signal as a function of the drive signal and the digital duty cycle signal, the delay control signal to represent a quantization error of the pulse width.

51. The control system of claim 39 wherein the regulated output is selected from the group comprising output voltage and output current.

52. The control system of claim 39 further comprising means for setting a nominal value of the regulated output.

53. The control system of claim 52 wherein the means for setting the nominal value further includes means for generating a reference signal in response to an input, the reference signal to set the nominal value of the regulated output.

54. The control system of claim 39 further comprising means for storing state information of the output regulator;

and

means for analyzing the stored state information.

55. The control system of claim 54 wherein the state information is selected from a group consisting of output voltage, output current, nominal duty cycle, adjusted duty cycle, power switch on-time, power switch off-time, and adjustment value.

56. The control system of claim 54 wherein the output regulator has a switching frequency;

and

further including means for capturing the state information at a rate greater than the switching frequency of the output regulator.

60. The control system of claim 39 wherein the drive signal controls the regulated output such that each of the at least three reference ranges results in a corresponding operating mode.

63. The control system of claim 39 wherein each of the at least three reference ranges has an upper limit and a lower limit, wherein a difference between the upper and lower limits of at least one of the at least three reference ranges is different than a difference between upper and lower limits of remaining ones of the at least three reference ranges.

45. The control system of 44 further including;

means for receiving an input pulse signal corresponding to the duty cycle estimation;

means for generating a plurality of delay signals referenced to the input pulse signal, each of the delay signals having a delay time;

means for selecting at least one of the delay signals;

means for combining the input pulse signal and the selected delay signal; and

means for generating the output pulse width signal based on the combining, the output pulse width signal to set a pulse width for the output regulator.

46. The control system of claim 45 wherein a relationship of the delay time of each of the at least four delay signals is selected from a group consisting of approximately equal, binary, and exponential.

47. The control system of claim 45 wherein the delay time of the selected delay signal is approximately equal to the pulse width error.

57. A control system for controlling an output regulator having a regulated output, comprising:

an output sensor to generate a digital sense signal to indicate within which of at least three reference ranges the regulated output is included, each of the at least three reference ranges including a plurality of possible values of the regulated output;

a digital controller, responsive to the digital sense signal, to generate a duty cycle estimation for estimating a duty cycle of a drive signal, the drive signal to control the power stage and thereby regulate the regulated output;

a duty cycle generator to generate the drive signal as a function of the duty cycle estimation, the duty cycle generator including;

a counter, responsive to a clock signal having a clock period, to generate the drive signal having a pulse width, the pulse width being approximately an integer multiple of the clock period, the counter including a counter limit input to receive a digital duty cycle signal corresponding to the duty cycle estimation, the digital duty cycle signal to set a quantity of clock periods to count such that the pulse width is approximately equal to the clock period multiplied by the digital duty cycle signal;

a delay line to finetune the pulse width of the drive signal based on the duty cycle estimation and a select signal representative of a quantization error corresponding to the clock period; and

a control block to generate the delay control signal in response to the drive signal and the digital duty cycle signal.

64. A control system for controlling an output regulator having a regulated output, comprising:

an output sensor to generate a digital sense signal to indicate within which of at least three reference ranges the regulated output is included; and

a digital controller, responsive to the digital sense signal, to generate a drive signal to control the regulated output,

wherein the drive signal controls the regulated output such that each of the at least three reference ranges results in a corresponding operating mode.

65. A method of controlling an output regulator having a regulated output, comprising:

generating a digital sense signal to indicate within which of at least three reference ranges the regulated output is included; and

generating a drive signal, in response to the digital sense signal, to control the regulated output,

wherein the drive signal controls the regulated output such that each of the at least three reference ranges results in a corresponding operating mode.

66. A control system for controlling an output regulator having a regulated output, comprising:

means for generating a digital sense signal to indicate within which of at least three reference ranges the regulated output is included; and

means for generating a drive signal, in response to the digital sense signal, to control the regulated output,

wherein the drive signal controls the regulated output such that each of the at least three reference ranges results in a corresponding operating mode.