Power system having a phase locked loop with a notch filter

• US 6,977,827 B2
• Filed: 03/22/2004
• Issued: 12/20/2005
• Est. Priority Date: 03/22/2004
• Status: Expired due to Fees

• Current Assignee: American Superconductor Corporation
• Original Assignee: American Superconductor Corporation
• Inventors: Gritter, David J.
• Primary Examiner(s): Riley, Shawn
• Application Number:
  US10/805,723
• Publication Number:
  US 20050207190A1
• Time in Patent Office: 638 Days
• Field of Search: 363/40, 363/41, 363/42, 323/207
• US Class Current: 363/40
• CPC Class Codes: H02M 1/12 Arrangements for reducing harmonics from ac input or output
• CPC Class Codes: H02M 7/53871 with automatic control of output voltage or current

Abstract

A power system having a phase locked loop (PLL) with a notch filter for synchronous reference frame sequence separation. The notch filter includes a generalized integrator tuned to the notch frequency. The output of the generalized integrator is summed with the filter input signal and the output of the summer is fed back to the integrator input. In one embodiment, the notch filter is programmable by a control signal generated in response to the filter output signal, thereby causing the filter to self-regulate to a frequency related to the PLL input signal. Illustrative power systems include active VAR generators and active rectifiers. One or more additional notch filters may be used to remove harmonic components from derived synchronous reference frame sequence components.

Claims

1. A power system associated with a three phase line comprising:

a three phase to two phase transformation processor responsive to the three phase line for generating two phase x and y axis sequence components;

a stationary to rotating reference frame converter responsive to the x and y axis sequence components and to an angle signal for generating rotating D and Q axis sequence components wherein the D and Q axis sequence components have a phase determined by the angle signal; and

a phase locked loop (PLL) responsive to a selected one of the rotating D and Q axis sequence components for generating the angle signal, wherein the PLL comprises a notch filter.

2. The power system of claim 1 wherein the PLL further comprises a regulator for regulating the selected one of the rotating D and Q axis sequence components to zero volts, wherein an output signal of the regulator provides an input signal to the notch filter.

3. The power system of claim 2 wherein the regulator is a proportional integral (PI) regulator.

4. The power system of claim 2 wherein the selected one of the D and Q axis sequence components is the D axis component.

5. The power system of claim 2 wherein the PLL further comprises an integrator for integrating an output signal of the notch filter to provide the angle signal.

6. The power system of claim 2 wherein the notch filter comprises:

a summer circuit having a first input port to which an the output of the regulator is coupled, a second input port, and an output port at which a filtered signal is provided; and

a generalized integrator having a first input port coupled to the output port of the summer circuit, a second input port responsive to a control signal, and an output port at which an error signal is provided, wherein the output port of the generalized integrator is coupled to the second input port of the summer circuit and wherein the generalized integrator is tuned to the frequency of the control signal.

7. The power system of claim 6 further comprising a circuit responsive to the filtered signal for generating the control signal so as to cause the notch filter to self regulate to a frequency related to the filter input signal.

8. The power system of claim 7 wherein the the circuit comprises a low pass filter.

9. The power system of claim 1 further comprising a second notch filter coupled to an output of the stationary to rotating reference frame converter for rejecting a harmonic component from at least one of the D and Q axis sequence components.

10. The power system of claim 1 wherein the power system is an active rectifier that is responsive to the three phase line voltage for generating a regulated DC bus voltage.

11. The power system of claim 1 wherein the power system is an active VAR generator and wherein the D and Q axis sequence components are used to generate current reference signals for controlling an inverter to inject energy into or withdraw energy from the three phase line in order to restore an AC line voltage to a specified level.

12. A notch filter comprising:

a summer circuit having a first input port to which a filter input signal is coupled, a second input port, and an output port at which a filtered signal is provided; and

a generalized integrator having a first input port coupled to the output port of the summer circuit, a second input port responsive to a control signal, and an output port at which an error signal is provided, wherein the output port of the generalized integrator is coupled to the second input port of the summer circuit and wherein the generalized integrator is tuned to the frequency of the control signal.

13. The filter of claim 12 further comprising a unit delay element coupled between the output port of the summer circuit and the first input port of the generalized integrator.

14. The filter of claim 12 further comprising an output gain element coupled to the output port of the summer circuit and a feedback gain element coupled between an output port of the unit delay element and the first input port of the generalized integrator.

15. The filter of claim 12 wherein the control signal has a level indicative of two times the frequency of a sampled AC line voltage.

16. The filter of claim 12 wherein the generalized integrator has a transfer function given by:

$\frac{s}{s^2+{\mathrm{\omega <br><br>}}^2}.$

17. A phase locked loop (PLL) for generating an angle signal for use in converting a stationary reference frame signal to a synchronous reference frame signal comprising:

regulator having an input port to which an input signal to the PLL is coupled and an output port;

a filter having an input port coupled to the output port of the regulator and an output port, said filter comprising;

a summer circuit having a first input port coupled to the output port of the PI regulator, a second input port, and an output port at which a filtered signal is provided; and

a generalized integrator having a first input port coupled to the output port of the summer circuit, a second input port responsive to a control signal, and an output port at which an error signal is provided, wherein the output port of the generalized integrator is coupled to the second input port of the summer circuit and wherein the generalized integrator is tuned to the frequency of the control signal; and

an integrator having an input port coupled to the output port of the filter and an output port at which the angle signal is provided.

18. A phase locked loop (PLL) for generating an angle signal for use in converting a stationary reference frame signal to a synchronous reference frame signal comprising:

a regulator responsive to an input signal for regulating the input signal to zero volts;

a notch filter having an input port coupled to an output port of said regulator and an output port at which a filtered signal is provided, said notch filter being tuned in response to a control signal; and

a circuit coupled to the output port of said notch filter and responsive to the filtered signal for generating said control signal, wherein the control signal has a level related to the frequency of the regulator input signal.

19. The PLL of claim 18 wherein the circuit comprises a low pass filter.

20. The PLL of claim 18 further comprising an integrator responsive to the filtered signal for generating the angle signal.