Bidirectional optical communications having quick data recovery without first establishing timing and phase lock
First Claim
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1. A method of transmitting and recovering a stream of coded data bits without establishing a timing or phase lock, comprising the steps of:
- generating a stream of data bits at a selected frequency, each bit of said stream of data bits having one portion at a first voltage level and another portion at a second voltage level;
generating a stream of clocking pulses at a second frequency, which second frequency is a multiple of said selected frequency;
coding said stream of data bits bysetting said one portion of each bit to a reference voltage level;
continuously switching said another portion of each bit between said reference voltage level and another voltage level different than said reference voltage level at said second frequency;
transmitting said coded data stream from a first location to another location;
receiving said coded data stream and providing said coded data stream to a delay circuit and a combining circuit;
delaying said coded data stream at said delay circuitry for a period of time substantially equal to one-half cycle of said second clocking frequency and providing said delayed coded data stream to said combining circuit; and
combining said coded data stream and said delayed coded data stream to recover said stream of data bits at said selected frequency.
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Abstract
A method of transmitting and rapidly recovering a burst of data without first having to establish a timing or phase lock. The signals are transmitted as modified Manchester coded signals having pulse transitions at a clocking pulse rate which is a multiple of the clocking pulse rate at which the signals are originally generated, and wherein the MOOSE coded signal is modified by ON-OFF keying.
15 Citations
13 Claims
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1. A method of transmitting and recovering a stream of coded data bits without establishing a timing or phase lock, comprising the steps of:
generating a stream of data bits at a selected frequency, each bit of said stream of data bits having one portion at a first voltage level and another portion at a second voltage level; generating a stream of clocking pulses at a second frequency, which second frequency is a multiple of said selected frequency; coding said stream of data bits by setting said one portion of each bit to a reference voltage level; continuously switching said another portion of each bit between said reference voltage level and another voltage level different than said reference voltage level at said second frequency; transmitting said coded data stream from a first location to another location; receiving said coded data stream and providing said coded data stream to a delay circuit and a combining circuit; delaying said coded data stream at said delay circuitry for a period of time substantially equal to one-half cycle of said second clocking frequency and providing said delayed coded data stream to said combining circuit; and combining said coded data stream and said delayed coded data stream to recover said stream of data bits at said selected frequency. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9)
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10. In a data transmission system wherein a stream of data bits having a selected frequency and a first portion at one voltage level and a second portion at a second voltage level is modified for transmission between a first location and another location by setting said first portion of said data bits to a reference voltage level and continuously switching said second portion between said reference voltage level and another voltage level different than said reference voltage level at a second clocking frequency which is a multiple of said selected frequency, a method of recovering said stream of data bits without establishing timing or phase lock comprising the steps of:
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receiving said modified stream of data bits and providing said modified stream to a delay circuit and a combining circuit; delaying said modified stream of data bits of said delay circuit for a period of time substantially equal to one-half cycle of said second clocking frequency and providing said delayed modified stream of data bits to said combining circuit; and combining said modified stream of data bits and said delayed modified stream of data bits to recover said stream of data bits having said selected frequency. - View Dependent Claims (11, 12, 13)
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Specification