Plug-and-play cable with protocol translation

• US 6,978,319 B1
• Filed: 08/18/2000
• Issued: 12/20/2005
• Est. Priority Date: 11/14/1997
• Status: Expired due to Term

• Current Assignee: Kawasaki MicroElectronics (Megachips Corporation)
• Original Assignee: Kawasaki MicroElectronics (Megachips Corporation)
• Inventors: Silverman, Joel, Rostoker, Michael D.
• Primary Examiner(s): Dinh, Dung C.
• Application Number:
  US09/642,282
• Time in Patent Office: 1,950 Days
• Field of Search: 709/250, 709/230, 709/246, 709/227, 710 70- 72, 710/63, 710/65
• US Class Current: 709/250
• CPC Class Codes: G06F 13/385 for adaptation of a particular data processing system to different peripheral devices
• CPC Class Codes: G06F 9/4411 Configuring for operating with peripheral devices; Loading of device drivers

Abstract

A protocol translation cable assembly includes a first connector having a first plurality of pins, a second connector having a second plurality of pins, and an electrical cable coupling the first connector to the second connector, where the electrical cable includes a plurality of conductors. The protocol translation cable assembly further includes translation circuitry coupled to at least some of the plurality of wires of the electric cable at points between the first plurality of pins of the first connector and the second plurality of pins of the second connector. The translation circuitry preferably derives its power from the electrical cable such that separate power supplies are not required. The cable assembly therefore provides transparent “plug-and-play” capabilities.

Claims

1. A method for plug-and-play compatibility between a first apparatus capable of digitally communicating with a first protocol through a first apparatus connector and a second apparatus capable of digitally communicating with a second protocol through a second apparatus connector, said method comprising:

determining a first communication protocol received at a first apparatus connector;

enabling a first protocol driver appropriate to said determined first protocol in a first protocol processor;

translating digital communications provided at a said first apparatus connector in said first protocol into digital communications at said second apparatus connector in said second protocol through said first protocol processor and then a second protocol processor; and

translating digital communications provided at said second apparatus connector in said second protocol into digital communications at said first apparatus connector in said first protocol through said second protocol processor and then said first protocol processor.

2. A method for plug-and-play compatibility as recited in claim 1, wherein enabling said first protocol driver includes selecting said first protocol driver from a collection of drivers stored in a memory coupled to said first protocol processor.

3. A method for plug-and-play compatibility as recited in claim 1, wherein enabling said first protocol driver includes downloading said first protocol driver through said first apparatus connector to a memory coupled to said first protocol processor.

4. A single chip protocol translator comprising:

a unitary semiconductor substrate integrating a translation circuitry; and

a memory coupled to said translation circuitry, wherein said translation circuitry is capable of communicating with first external devices with a first protocol and with second external devices with a second protocol, said first protocol being different from said second protocol, and wherein said first protocol is implemented with a first driver stored in said memory and said second protocol is implemented with a second driver stored in said memory.

5. A single chip protocol translator as recited in claim 4, wherein said memory stores a collection of drivers, and wherein said translation circuitry selects an appropriate driver for at least one of said first driver and second driver selected from said collection of drivers.

6. A single chip protocol translator as recited in claim 4, wherein at least one of said first driver and said second driver is loaded into said memory from at least one of said first external drivers and said second external drivers.

7. A single chip protocol translator as recited in claim 4, wherein said memory stores a collection of drivers, and wherein said translation circuitry determines at least one of said first protocol and said second protocol, and selects at least one selected driver for at least one of said first driver and said second driver appropriate to said determined at least one of said first protocol and said second protocol from said collection of drivers.

8. A method for plug-and-play compatibility of a protocol translation circuitry, said method comprising:

determining a first communication protocol received at a first group of terminals of said protocol translation circuitry;

enabling a first protocol driver appropriate to said determined first protocol in a first protocol processor within said translation circuitry;

translating digital communications in said first protocol provided at said first group of terminals into digital communications in a second protocol at a second group of terminals through said first protocol processor and then a second protocol processor; and

translating digital communications in said second protocol provided at said second group of terminals into digital communications in said first protocol at said first group of terminals through said second processor and then said first protocol processor.

9. A method for plug-and-play compatibility as recited in claim 8, wherein enabling said first protocol driver includes selecting said first protocol driver from a collection of drivers stored in memory coupled to said protocol processor.

10. A method for plug-and-play compatibility as recited in claim 8, wherein enabling said first protocol driver includes downloading said first protocol driver through said first group of terminals to a memory coupled to said first protocol processor.

11. A protocol translation circuitry for plug-and-play compatibility, comprising:

a first group of terminals for receiving first digital communications in a first protocol;

a second group of terminals for receiving second digital communications in a second protocol;

a first protocol processor coupled to said first group of terminals; and

a second protocol processor coupled to said second group of terminals, wherein said first protocol processor determines said first protocol received at said first group of terminals and enables in said first protocol processor a first driver appropriate to said determined first protocol, and wherein said first digital communications provided at said first group of terminals in said first protocol are translated through said first protocol processor and then said second protocol processor into translated first digital communications in said second protocol at said second group of terminals, and said second digital communications received at said second group of terminals in said second protocol are translated through said second protocol processor and then said first protocol processor into translated second digital communications in said first protocol at said first group of terminals.

12. A protocol translation circuitry as recited in claim 11, further comprising a memory coupled to said first protocol processor, wherein said memory stores a collection of protocol drivers, and said first protocol processor selects said first protocol driver from said collection of protocol drivers.

13. A protocol translation circuitry as recited in claim 11, further comprising a memory coupled to said first protocol processor, wherein said first protocol driver is loaded through said first group of terminals into said memory.

14. A cable assembly for plug-and-play capability between a first apparatus capable of digitally communicating with a first protocol through a first apparatus connector and a second apparatus capable of digitally communicating with a second protocol through a second apparatus connector, comprising:

a first cable connector adapted to be coupled to said first apparatus connector;

a second cable connector adapted to be coupled to said second apparatus connector;

an electrical cable coupling said first cable connector to said second cable connector, said electrical cable including a plurality of conductors;

a translation circuitry for translating digital communications provided at said first apparatus connector in said first protocol into digital communications at said second apparatus connector in said second protocol, and for translating digital communications provided at said second apparatus connector in said second protocol into digital communications at said first apparatus connector in said first protocol, wherein said translation circuitry determines said first protocol and enables a first protocol driver appropriate to said determined first protocol in said translation circuitry.

15. A cable assembly as recited in claim 14, wherein said translation circuitry includes a memory that stores a collection of protocol drivers, and said translation circuitry selects said first protocol driver from said collection of protocol drivers.

16. A cable assembly as recited in claim 14, wherein said translation circuitry includes a memory, and said first protocol driver is loaded through said first cable connector into said memory.

17. A protocol translator for plug-and-play compatibility, comprising:

a first group of terminals for receiving first digital communications in a first protocol;

a second group of terminals for receiving second digital communications in a second protocol; and

a translation circuitry provided between said first group of terminals and said second group of terminals, wherein said translation circuitry determines said first protocol received at said first group of terminals and enables a first protocol driver appropriate to said determined first protocol in said translation circuitry, such that said translation circuitry translates said first digital communications in said first protocol provided at said first group of terminals into translated first digital communications in said second protocol at said second group of terminals, and also translates said second digital communications in said second protocol provided at said second group of terminals into translated second digital communications in said first protocol at said first group of terminals.

18. A protocol translator as recited in claim 17, further comprising a memory coupled to said translation circuitry, wherein said memory stores a collection of protocol drivers, and said translation circuitry selects said first protocol driver from said collection of drivers.

19. A protocol translator as recited in claim 17, further comprising a memory coupled to said translation circuitry, wherein said first protocol driver is loaded through said first group of terminals into said memory.

20. A method for plug-and-play compatibility of a protocol translation circuitry, said method comprising:

determining a first communication protocol received at a first group of terminal of said translation circuitry;

enabling a first protocol driver appropriate to said determined first protocol in said translation circuitry;

translating digital communications in said first protocol provided at said first group of terminals into digital communications in a second protocol at a second group off terminals through said translation circuitry; and

translating digital communications in said second protocol provided at said second group of terminals into digital communications in said first protocol at said first group of terminals through said translation circuitry.

21. A method for plug-and-play compatibility as recited in claim 20, wherein enabling said first protocol driver includes selecting said first protocol driver from a collection of drivers stored in a memory coupled to said translation circuitry.

22. A method for plug-and-play compatibility as recited in claim 20, wherein enabling said first protocol driver includes downloading said first protocol driver through said first group of terminals to a memory coupled to said translation circuitry.