Serial ATA controller having failover function

• US 6,978,337 B1
• Filed: 12/02/2002
• Issued: 12/20/2005
• Est. Priority Date: 12/02/2002
• Status: Expired due to Term

• Current Assignee: Marvell Asia Pte Limited (Marvell Technology Group Limited)
• Original Assignee: Marvell International Limited (Marvell Technology Group Limited)
• Inventors: Chang, Po-Chien
• Primary Examiner(s): Perveen, Rehana
• Assistant Examiner(s): Mason, Donna K.
• Application Number:
  US10/307,845
• Time in Patent Office: 1,114 Days
• Field of Search: 710305-306, 710312-313, 710315-316
• US Class Current: 710/306
• CPC Class Codes: G06F 11/2089 Redundant storage control functionality
• CPC Class Codes: G06F 3/0601 Interfaces specially adapted for storage systems
• CPC Class Codes: G06F 3/0673 Single storage device

Abstract

A select circuit including a first device bridge to communicate a first stream of information between a first Serial ATA bus and a storage device bus. A second device bridge to communicate a second stream of information between a second Serial ATA bus and the storage device bus. A controller, in response to a select signal, to enable one of the first bridge device and the second bridge device to control a flow of the first stream of information and the second stream of information between the storage device bus and the first and second Serial ATA buses.

Claims

1. A system comprising:

a first serial Advanced Technology Attachment (ATA) bus;

a second serial ATA bus;

a parallel ATA storage device bus;

a select circuit that communicates with said first and second serial ATA buses and said parallel ATA storage device bus and that comprises;

a first device bridge that bidirectionally converts a first serial data stream on the first serial ATA bus to a parallel data stream on the parallel ATA storage device bus;

a second device bridge that bidirectionally converts a second serial data stream on the second serial ATA bus to said parallel data stream on the parallel ATA storage device bus; and

a controller that selectively enables one of said first device bridge and said second device bridge to control data flow between the first and second serial ATA buses and the parallel ATA storage device bus.

2. The system of claim 1 wherein said controller selectively enables said first and second device bridges based on a select signal that includes a first signal corresponding to said first device bridge and a second signal corresponding to said second device bridge.

3. The system of claim 2 wherein said first signal has an enable state and a disable state, said second signal has an enable state and a disable state, and said controller enables said second device bridge when said second signal is in said enable state.

4. The system of claim 2 wherein said controller enables said first device bridge when said first signal is in said enable state and said second signal is in said disable state.

5. The system of claim 2 wherein said first signal is in either of said enable state and said disable state.

6. The system of claim 1 wherein said controller generates a first enable signal to control said first device bridge and a second enable signal to control said second device bridge.

7. A system comprising:

first and second serial Advanced Technology Attachment (ATA) buses;

a parallel ATA storage device bus;

first bridge means for bidirectionally converting a first serial data stream on the first serial ATA bus to a parallel data stream on the parallel ATA storage device bus;

second bridge means for bidirectionally converting a second serial data stream on the second serial ATA bus to said parallel data stream on the parallel ATA storage device bus; and

control means for selectively enabling one of the first bridge means and the second bridge means to control data flow between the parallel ATA storage device bus and the first and second serial ATA buses.

8. The system of claim 7 wherein said control means selectively enables said first and second bridge means based on a select signal that includes a first signal corresponding to said first bridge means and a second signal corresponding to said second bridge means.

9. The system of claim 8 wherein said first signal has an enable state and a disable state, said second signal has an enable state and a disable state, and said control means enables said second bridge means when said second signal is in said enable state.

10. The system of claim 8 wherein said control means enables said first bridge means when said first signal is in said enable state and said second signal is in said disable state.

11. The system of claim 8 wherein said first signal is in either of said enable state and said disable state.

12. The system of claim 7 wherein said control means generates a first enable signal to control said first bridge means and a second enable signal to control said second bridge means.

13. A method for selecting an input/output path, comprising:

bidirectionally converting a first serial data stream on the first serial Advanced Technology Attachment (ATA) bus to a parallel data stream on a parallel ATA storage device bus;

bidirectionally converting a second serial data stream on a second serial ATA bus to said parallel data stream on the parallel ATA storage device bus; and

selectively enabling data flow between the first and second serial ATA buses and the parallel ATA storage device bus.

14. The method of claim 13 further comprising generating a first signal to enable a first device bridge and a second signal to enable a second device bridge.

15. The method of claim 14 wherein said first signal has an enable state and a disable state, said second signal has an enable state and a disable state, and further comprising enabling said second device bridge when said second signal is in said enable state.

16. The method of claim 14 further comprising enabling said first device bridge when said first signal is in said enable state and said second signal is in said disable state.

17. The method of claim 14 wherein said first signal is in either of said enable state and said disable state.

18. The method of claim 13 further comprising generating a first enable signal to control said first device bridge and a second enable signal to control said second device bridge.

19. A select circuit, comprising:

a first device bridge that bidirectionally converts a first serial data stream on a first serial Advanced Technology Attachment (ATA) bus to a parallel data stream on a parallel ATA storage device bus;

a second device bridge that bidirectionally converts a second serial data stream on a second serial ATA bus to said parallel data stream on the parallel ATA storage device bus; and

a controller that selectively enables one of said first device bridge and said second device bridge to control data flow between the first and second serial ATA buses and the parallel ATA storage device bus.

20. The select circuit of claim 19 wherein said controller selectively enables said first and second device bridges based on a select signal that includes a first signal corresponding to said first device bridge and a second signal corresponding to said second device bridge.

21. The select circuit of claim 20 wherein said first signal has an enable state and a disable state, said second signal has an enable state and a disable state, and said controller enables said second device bridge when said second signal is in said enable state.

22. The select circuit of claim 20 wherein said controller enables said first device bridge when said first signal is in said enable state and said second signal is in said disable state.

23. The select circuit of claim 20 wherein said first signal is in either of said enable state and said disable state.

24. The select circuit of claim 19 wherein said controller generates a first enable signal to control said first device bridge and a second enable signal to control said second device bridge.

25. A select circuit, comprising:

first bridge means for bidirectionally converting a first serial data stream on a first serial ATA bus to a parallel data stream on a parallel ATA storage device bus;

second bridge means for bidirectionally converting a second serial data stream on a second serial ATA bus to said parallel data stream on the parallel ATA storage device bus; and

control means for selectively enabling one of the first bridge means and the second bridge means to control data flow between the parallel ATA storage device bus and the first and second serial ATA buses.

26. The select circuit of claim 25 wherein said control means selectively enables said first and second bridge means based on a select signal that includes a first signal corresponding to said first bridge means and a second signal corresponding to said second bridge means.

27. The select circuit of claim 26 wherein said first signal has an enable state and a disable state, said second signal has an enable state and a disable state, and said control means enables said second bridge means when said second signal is in said enable state.

28. The select circuit of claim 26 wherein said control means enables said first bridge means when said first signal is in said enable state and said second signal is in said disable state.

29. The select circuit of claim 26 wherein said first signal is in either of said enable state and said disable state.

30. The select circuit of claim 25 wherein said control means generates a first enable signal to control said first bridge means and a second enable signal to control said second bridge means.