Photomask for eliminating antenna effects in an integrated circuit and integrated circuit manufacture with same
First Claim
1. A photomask, comprising:
- a substrate; and
a patterned layer formed on at least a portion of the substrate, the patterned layer formed using a mask pattern file created by;
analyzing a pattern in a mask layout file to identify a region including an antenna ratio less than a first design rule;
moving a feature located in the identified region from a first position to a second position in the mask layout file to create a space in the identified region for placing a grounding feature, the second position selected by using a second design rule to prevent a physical layout violation from being created when moving the feature from the identified region;
placing the grounding feature in the space; and
automatically connecting the grounding feature to a gate feature in the mask layout file such that the antenna ratio is increased to greater than or approximately equal to the first design rule.
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0 Petitions
Accused Products
Abstract
A photomask for eliminating antenna effects in an integrated circuit and integrated circuit manufactured with the photomask are disclosed. The photomask includes a substrate and a patterned layer formed on at least a portion of the substrate. The patterned layer may be formed using a mask pattern file created by analyzing a pattern in a mask layout file to identify a region including an antenna ratio less than a first design rule. A feature located in the identified region is moved based on a second design rule from a first position to a second position in the mask layout file to create a space in the identified region. A grounding feature is placed in the space and automatically connected to a gate feature in the mask layout file such that the antenna ratio is increased to greater than or approximately equal to the first design rule.
318 Citations
22 Claims
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1. A photomask, comprising:
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a substrate; and a patterned layer formed on at least a portion of the substrate, the patterned layer formed using a mask pattern file created by; analyzing a pattern in a mask layout file to identify a region including an antenna ratio less than a first design rule; moving a feature located in the identified region from a first position to a second position in the mask layout file to create a space in the identified region for placing a grounding feature, the second position selected by using a second design rule to prevent a physical layout violation from being created when moving the feature from the identified region; placing the grounding feature in the space; and automatically connecting the grounding feature to a gate feature in the mask layout file such that the antenna ratio is increased to greater than or approximately equal to the first design rule. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10)
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11. A photomask assembly, comprising:
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a pellicle assembly defined in part by a pellicle frame and a pellicle film attached thereto; and a photomask coupled to the pellicle assembly opposite from the pellicle film, the photomask including a patterned layer formed on a substrate, the patterned layer formed using a mask pattern file created by; analyzing a pattern in a mask layout file to identify a region including an antenna ratio less than a first design rule; moving a feature located in the identified region from a first position to a second position in the mask layout file to create a space in the identified region for placing a grounding feature, the second position selected by using a second design rule to prevent a physical layout violation from being created when moving the feature from the identified region; placing the grounding feature in the space; and automatically connecting the grounding feature to a gate feature in the mask layout file such that the antenna ratio is increased to greater than or approximately equal to the first design rule. - View Dependent Claims (12, 13, 14, 15, 16)
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17. An integrated circuit formed on a semiconductor wafer, comprising:
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a plurality of interconnect layers selected from a group consisting of n-well, p-well, diffusion, polysilicon and metal; and a plurality of contact layers operable to provide electrical connections between the interconnect layers; the interconnect and contact layers formed on a semiconductor wafer using a plurality of photomasks created by; analyzing a pattern in a mask layout file to identify a region including an antenna ratio less than a first design rule; moving a feature located in the identified region from a first position to a second position in the mask layout file to create a space in the identified region for placing a grounding feature, the second position selected by using a second design rule to prevent a physical layout violation from being created when moving the feature from the identified region; placing the grounding feature in the space; and automatically connecting the grounding feature to a gate feature in the mask layout file such that the antenna ratio is increased to greater than or approximately equal to the first design rule. - View Dependent Claims (18, 19, 20, 21, 22)
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Specification