Connection of integrated circuits

• US 6,979,591 B2
• Filed: 05/28/2003
• Issued: 12/27/2005
• Est. Priority Date: 05/28/2002
• Status: Expired due to Fees

• Current Assignee: Polaris Innovations Limited (Wi-LAN Inc.)
• Original Assignee: Infineon Technologies AG
• Inventors: Hedler, Harry, Irsigler, Roland, Pohl, Jens
• Primary Examiner(s): Schillinger, Laura M.
• Assistant Examiner(s): MITCHELL, JAMES M
• Application Number:
  US10/446,396
• Publication Number:
  US 20040012080A1
• Time in Patent Office: 944 Days
• Field of Search: 438/613, 438/612, 438/107, 438/108, 438/118, 438/119, 438/106, 257/777, 257/778, 257/686
• US Class Current: 438/107
• CPC Class Codes: H01L 2224/023 Redistribution layers [RDL] for bonding areas
• CPC Class Codes: H01L 2224/05569 the external layer being disposed on a redistribution layer on the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/05573 Single external layer
• CPC Class Codes: H01L 2224/0615 Mirror array, i.e. array having only a reflection symmetry, i.e. bilateral symmetry
• CPC Class Codes: H01L 2224/13 of an individual bump connector
• CPC Class Codes: H01L 2224/13099 Material
• CPC Class Codes: H01L 2224/16145 the bodies being stacked
• CPC Class Codes: H01L 2224/32145 the bodies being stacked
• CPC Class Codes: H01L 2224/32225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48227 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/48471 the other connecting portion not on the bonding area being a ball bond, i.e. wedge-to-ball, reverse stitch
• CPC Class Codes: H01L 2224/73265 Layer and wire connectors
• CPC Class Codes: H01L 2225/0651 Wire or wire-like electrical connections from device to substrate
• CPC Class Codes: H01L 2225/06513 Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
• CPC Class Codes: H01L 2225/06527 Special adaptation of electrical connections, e.g. rewiring, engineering changes, pressure contacts, layout
• CPC Class Codes: H01L 2225/06586 Housing with external bump or bump-like connectors
• CPC Class Codes: H01L 23/3128 the substrate having spherical bumps for external connection
• CPC Class Codes: H01L 24/10 Bump connectors bumps on insulating substrates, e.g. chip carriers, H01L23/49816; Manufacturing methods related thereto
• CPC Class Codes: H01L 24/13 of an individual bump connector
• CPC Class Codes: H01L 25/0657 : Stacked arrangements of devices
• CPC Class Codes: H01L 25/50 : Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00 H01L21/50 takes precedence
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0001 : Technical content checked by a classifier
• CPC Class Codes: H01L 2924/00012 : Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01005 : Boron [B]
• CPC Class Codes: H01L 2924/01006 : Carbon [C]
• CPC Class Codes: H01L 2924/01015 : Phosphorus [P]
• CPC Class Codes: H01L 2924/01019 : Potassium [K]
• CPC Class Codes: H01L 2924/01022 : Titanium [Ti]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01059 : Praseodymium [Pr]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/181 : Encapsulation
• CPC Class Codes: H01L 2924/30105 : Capacitance
• CPC Class Codes: H01L 2924/30107 : Inductance

Abstract

A method for connecting a first integrated circuit having an elevated contact area lying on an elastic elevation on a main area thereof and a second integrated circuit having a corresponding non-elevated contact area on a main area thereof includes applying a liquid adhesive between the first and second main areas; aligning the first and second main areas so that the elevated contact area is opposite the corresponding non-elevated contact area; and curing the adhesive, thereby firmly connecting the first and second integrated circuits.

Claims

1. A method for connecting a first integrated circuit and a second integrated circuit, the method comprising:

providing a plurality of first integrated circuits, each of which includes a first wiring device on a first main surface, and a corresponding plurality of second integrated circuits, each of which includes a second wiring device on a second main surface, the plurality of first integrated circuits and the plurality of second integrated circuits being in the form of chip pairs;

wherein one of the first and second wiring devices comprises a plurality of elevated contact areas lying on respective elastic elevations and wherein the other of the first and second wiring devices comprises a plurality of non-elevated contact areas that can be aligned to the elevated contact areas;

mounting the first integrated circuits onto a substrate;

dispensing a liquid adhesive on at least one of the first and second main surfaces;

aligning the first and second main areas so that the elevated contact area and the corresponding non-elevated contact area are brought into electrical contact;

pressing said first and second main areas by simultaneously applying pressure onto the plurality of second integrated circuits using a pressure plate, such that the elevated contact areas are deformed; and

curing the adhesive, thereby firmly connecting the first and second integrated circuits, wherein curing the adhesive includes at least partially curing the adhesive while the elevated contact area is deformed such that the elevated contact area remains deformed subsequent to connecting the first and second integrated circuits.

2. The method of claim 1, further comprising providing a bonding wire in electrical communication with a contact area on the substrate and a contact area on the first circuit device.

3. The method of claim 1, further comprising selecting at least one of the first and second integrated circuits to be in wafer form.

4. The method of claim 1, further comprising selecting at least one of the first and second integrated circuits to be in chip form.

5. The method of claim 1, further comprising selecting at least one of the first and second integrated circuits to be in the form of a hybrid of a wafer and a chip.

6. The method of claim 1, further comprising connecting the elevated contact area and the non-elevated contact area with solder.

7. The method of claim 1, further comprising connecting the elevated contact area and the non-elevated contact area with an electrically conducting adhesive.

8. The method of claim 1, further comprising, prior to aligning, connecting contact areas on the substrate to contact areas on an edge region of the first main surface by bonding wires such that the bonding wires are embedded in a respective space between said first and second integrated circuits in the adhesive.

9. The method of claim 1, wherein the elevated contact areas are connected to the non-elevated contact areas by at least one of solder and an electrically conductive adhesive.