Solid-state device

• US 6,979,877 B1
• Filed: 09/27/1994
• Issued: 12/27/2005
• Est. Priority Date: 09/28/1965
• Status: Expired due to Fees

• Current Assignee: Chou H. Li
• Original Assignee: Chou H. Li
• Inventors: Li, Chou H.
• Primary Examiner(s): CRANE, SARA W
• Application Number:
  US08/313,350
• Time in Patent Office: 4,109 Days
• Field of Search: 257/510, 257/622, 257/653
• US Class Current: 257/510
• CPC Class Codes: H01L 21/76232 of trenches having a shape other than rectangular or V-shape, e.g. rounded corners, oblique or rounded trench walls H01L21/76229 takes precedence
• CPC Class Codes: H01S 5/024 Arrangements for thermal management
• CPC Class Codes: H01S 5/02423 Liquid cooling, e.g. a liquid cools a mount of the laser

Abstract

A method of making dielectrically isolated solid state device comprising state device (including integrated circuits) comprises providing a silicon wafer having a PN junction or other electronic rectifying barrier contained therein and thermally growing or ion-implanting selected ions to an oxide or nitride isolating groove in-situ to isolate it into a plurality of physically integral pockets for use as electrically separately operable components. The groove has a symmetrical, centrally rounded bottom which is located within a few microns below the PN junction or rectifying barrier. Through the unique oxide/nitride forming conditions and through curvature, symmetry, and proximity effects, novel passivation and isolation results obtain.

Claims

1. A solid state circuit device comprising:

a solid state material substrate of one conductivity type having a first surface;

a solid state material body of opposite conductivity type placed on a selected area of the first surface of said substrate;

an electronic rectifying barrier region extending generally laterally along a part of the device where said substrate adjoins said body;

at least one groove filled with a material which is significantly different in electrical conductivity from material of at least one of said substrate and body under both a forward and a reverse voltage applied onto the interfacial electronic rectifying barrier region; and

said at least one groove comprising a protruding portion having a designed submicron width or thickness within one micron of at least one of said body and substrate.

2. A circuit device of claim 1 in which said substrate has a flat bottom major surface;

said at least one groove starts at a first end of a first side thereof, terminates at a first boundary of said protruding portion, and continues at a second boundary of said protruding portion along a second side, and toward a second end of a second side, of said at least one groove; and

normal distances to said flat bottom major surface of said substrate change monotonously from each of said first and second ends of the two sides to said protruding portion.

3. A circuit device of claim 1 in which:

said at least one groove has a first side and a second side thereof; and

said first side in its entity has only a positive slope while said second in its entity has only a negative slope.

4. The circuit device of claim 1 in which said at least one groove consists only of a single groove having two sides;

a first side starting at a first end of a first side of said at least one groove, and moving monotonously in one direction on said first side toward, and terminating at a first boundary of said protruding portion; and

a second side starting at a second end of a second side of said at least one groove, and moving monotonously in an opposite direction on said second side toward, and terminating also at a second boundary of said protruding portion.

5. The circuit device of claim 1 in which said at least one groove has two sides terminating at two respective ends of said two sides in a single protruding tip which divides, with a planer dividing plane, a first groove side from a second groove side;

normal distances between said dividing plane and both said groove sides increasing monotonously from the single protruding tip toward both ends of said respective groove sides.

6. The circuit device of claim 1 in which said at least one groove has a central major-portion rounded bottom consisting essentially of a 100% dense, pure solid material metallurgically continuously bonded onto at least one of said substrate, body, and said electronic rectifying barrier region.

7. The circuit device of claim 1 in which said electronic rectifying barrier region is selected from the group consisting of PN junction electronic rectifying barrier region, metal-semiconductor electronic rectifying barrier region, oxide-semiconductor barrier region, interfacial rectifying barrier region, heterojunction rectifying barrier region between different semiconductor materials, and other optoelectromagnetically active signal-translating region.

8. The circuit device of claim 1 which is mass-produced and in which a tip of the protruding portion of said at least one groove is within a vertical distance from a designated point inside said electronic rectifying barrier;

and

said vertical distance is selected from the group consisting of 1.0 micron (“

h=1 micron”

), 0.1 microns, and 0 microns (i.e., “

h_m=0”

).

9. The circuit device of claim 1 which is mass-produced and in which the protruding portion of said at least one groove terminates in a single protruding tip;

said protruding tip and a designated point inside the electronic rectifying barrier region is seperated by a 0.0 micron distance locally normally of the rectifying barrier region.

10. The circuit device of claim 1 which is mass-produced and in which the protruding portion of said at least one groove terminates in a single protruding tip;

said protruding tip and a designated point inside the electronic rectifying barrier region is seperated by a distance locally normally of said rectifying barrier region; and

said distance being significantly less than 0.1 microns and as close to zero as possible to give maximum protection against Type I contaminants.

11. The circuit device of claim 5 in which said protruding tip and a designated point inside the electronic rectifying barrier region is seperated by a distance substantially less than 0.1 micron and close-to-zero micron locally normally of the rectifying barrier region.

12. The circuit device of claim 1 which is mass-produced and in which the protruding portion of said at least one groove terminates in a single protruding tip;

said protruding tip having a close to zero distance normally of the rectifying barrier region because of a microscopically precise groove and configuration achieving 0.1 micron accuracy in shape, size, depth and location thereby providing sufficient device yield to be competitive and commercially profitable.

13. The circuit device of claim 1 in the form of a semiconductor circuit device in which:

said solid state material substrate is a semiconductor material substrate;

said solid state material body is a semiconductor material body; and

said electronic rectifying barrier region is a PN junction region.

14. The circuit device of claim 1 in which material of at least one of said substrate and body is selected from the group consisting of Si, Ge, diamond, SiC, InSb, GaAs, GaP, InP, III-V compounds, II-VI compounds, and mixture therof.

15. The circuit device of claim 1 in which said at least one groove is filled with a solid material which is orders of magnitude lower in electrical conductivity compared to those of materials of said substrate and body under any forward and reverse applied voltage on the interfacial rectifying barrier region.

16. The circuit device of claim 1 in which said at least one groove is filled with a solid, electrically insulating chemical compound of a semiconductor material.

17. The circuit device of claim 1 in which said at least one groove is filled with a solid, said solid metallurgically perfectly and continuously bonded to at least one of said substrate and body as to be free in the bonding region of defects including voids and microcracks visible at 1,000 times magnification.

18. The circuit device of claim 1 in which said at least one groove is filled with a solid and said solid is bonded to at least one of said substrate and body with a bonding region which comprises a graded seal having gradual chemical composition concentration changes so that high stress generated during device processing are spread out over wide areas providing stress relief and avoiding splitting cracks.

19. The circuit device of claim 1 in which said at least one groove comprises a first protruding portion having the designated submicron width or thickness;

said device including a second groove with a second protruding portion and a protruding direction of said first protruding portion being parallel to that of said second protruding portion.

20. The circuit device of claim 1 in which said at least one groove contacts at least one of said substrate, body, and electronic rectifying barrier region;

said device including a second groove with a second protruding portion with a second designed submicron width or thickness; and

protruding direction of said first and second protruding portions being selected from the group consisting of a) horizontal;

b) vertical; and

c) inclined to both horizontal and vertical.

21. The circuit device of claim 1 in which said at least one groove is an elongated hole or slot of a constant lateral cross-section and having an aspect or length/width ratio of over 2.5.

22. The circuit device of claim 1 in which the protruding portion of said at least one groove is major-portion rounded at a protruding tip of said protruding portion;

and

said protruding tip having a substantially zero width or thickness.

23. A solid state circuit device comprising:

a solid state material substrate of one conductivity type having a first surface;

a solid state material body of opposite conductivity type placed on a selected area of the first surface of said substrate;

an electronic rectifying barrier region extending generally laterally along a part of the device where said substrate adjoins said body;

said electronic rectifying barrier region having a beneficial residual stress therein to favorably affect characteristics of said circuit device; and

at least one groove filled with a material which is significantly different in electrical conductivity material of at least one of said substrate and body under both a forward and a reverse applied voltage on the interfacial rectifying barrier region; and

said at least one groove comprising a solid protruding portion having a designed submicron width or thickness within one micron of at least one of said body and substrate.

24. The circuit device of claim 23 in which said at least one groove is filled with a material which is electronically inert, pure, 100% dense, gas impervious, and non-contaminated to said electronic rectifying barrier region.

25. A solid state circuit device comprising:

a solid state material substrate of one conductivity type having a first surface;

a solid state material body of opposite conductivity type placed on a selected area of the first surface of said substrate;

an electronic rectifying barrier region extending generally laterally along a part of the device where said substrate adjoins said body; and

at least one groove having a single smooth-translating curvature and filled with a non-semiconductor material which is orders of magnitude different in electrical conductivity from those of materials of said substrate and body under both a forward and a reverse applied voltage on the interfacial rectifying barrier region;

said at least one groove comprising solid protruding portion having a designed submicron width or thickness within one micron of at least one of said body and substrate.

26. A solid state circuit device comprising:

a solid state material substrate of one conductivity type having a first surface;

a solid state material body of opposite conductivity type placed on a selected area of the first surface of said substrate;

an electronic rectifying barrier region extending generally laterally along a part of the device where said substrate adjoins said body;

at least one groove filled with a non-semiconductor material, adjoining at least one of said substrate, body, and electronic rectifying barrier region, and having a designated, submicron-accurate geometry, with respect to the electronic rectifying barrier to withstand process-induced stresses making the circuit device mechanically more stable and reliable;

said at least one groove comprising a solid protruding portion having a designated submicron width or thickness within one micron of at least one of said body and substrate.

27. A solid state circuit device comprising:

a solid state material substrate having a first surface;

a solid state material body placed on a selected area of the first surface of said substrate;

said substrate and said body forming an electronic signal-translating region extending at least generally laterally along a part of the device where said substrate adjoins said body, and

at least one groove of a solid, non-semiconductor material adjoining at least one of said substrate, body and electrical rectifying barrier region, and having a designated submicron-accurate geometry location and position relative to the electrical rectifying barrier region;

said electronic signal-translating region being curved in a way selected from;

a) substantial portion curved;

b) major portion curved;

c) major central portion curved;

d) curved in its entirety; and

e) concavely curved when viewed from the top;

said at least one groove comprising a solid protruding portion having a designed submicron width of thickness within one micron of at least one of said body and substrate.

28. The circuit device of claim 27 in which said electronic signal-translating region is a PN junction region and said groove is a cylindrical groove and is electrically conductive under both forward and reverse applied bias.