Package substrate for improving electrical performance

• US 6,979,897 B2
• Filed: 04/09/2004
• Issued: 12/27/2005
• Est. Priority Date: 04/17/2003
• Status: Active Grant

• Current Assignee: Advanced Semiconductor Engineering Inc (ASE Technology Holding Co., Ltd.)
• Original Assignee: Advanced Semiconductor Engineering Inc (ASE Technology Holding Co., Ltd.)
• Inventors: Ma, Shu-Jung
• Primary Examiner(s): Loke, Steven
• Assistant Examiner(s): Gebremariam, Samuel A.
• Application Number:
  US10/820,765
• Publication Number:
  US 20040207067A1
• Time in Patent Office: 627 Days
• Field of Search: 257/774, 257/784, 257/786, 257/691, 257/692, 257/698, 257/700
• US Class Current: 257/691
• CPC Class Codes: H01L 2224/05599 Material
• CPC Class Codes: H01L 2224/32225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/45099 Material
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48227 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/49 of a plurality of wire connectors
• CPC Class Codes: H01L 2224/73265 Layer and wire connectors
• CPC Class Codes: H01L 23/49822 Multilayer substrates multilayer metallisation on monolayer substrate H01L23/498
• CPC Class Codes: H01L 23/49827 Via connections through the substrates, e.g. pins going through the substrate, coaxial cables H01L23/49822, H01L23/49833, H01L23/4985, H01L23/49861 take precedence
• CPC Class Codes: H01L 23/49838 Geometry or layout
• CPC Class Codes: H01L 23/50 for integrated circuit devices, e.g. power bus, number of leadsH01L23/482 - H01L23/498 take precedence
• CPC Class Codes: H01L 24/48 of an individual wire connector
• CPC Class Codes: H01L 24/49 of a plurality of wire connectors
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01006 Carbon [C]
• CPC Class Codes: H01L 2924/01029 Copper [Cu]
• CPC Class Codes: H01L 2924/014 Solder alloys
• CPC Class Codes: H01L 2924/15173 in a single layer of the multilayer substrate

Abstract

A package substrate for improving electrical performance includes at least an insulating layer, a wiring layer and a ground/power layer. The wiring layer is formed on a top surface of the insulating layer, and includes a plurality of inner fingers, a plurality of outer fingers and a metal ring. A plurality of inner through holes are formed through the insulating layer to electrically connect corresponding inner fingers to bottom surface of the insulating layer. The ground/power layer has a plurality of openings formed on a bottom surface of the insulating layer. The plurality of inner through holes are crowded in groups to pass through the openings which are electrically isolated from the ground/power layer. Each group of the inner through holes are arranged in grid array or radial arrangement so that a distance between two adjacent openings not less than 0.2 mm for improving electrical performance of the ground/power layer.

Claims

1. A package substrate for improving electrical performance comprising:

a first insulating layer having a top surface and a bottom surface;

a plurality of groups of inner fingers formed on the top surface of the first insulating layer for electrically connecting to a chip;

a plurality of outer fingers formed on the top surface of the first insulating layer for electrically connecting to the chip;

a plurality of outer through holes formed through the first insulating layer and electrically connected to the corresponding outer fingers;

a plurality of inner through holes formed through the first insulating layer and electrically connected to the corresponding inner fingers; and

a ground/power layer located on the bottom surface of the first insulating layer, and having a plurality of openings, wherein a group of the inner through holes including at least two of the inner through holes passes through and is corresponding to one of the plurality of openings to be electrically isolated from the ground/power layer.

2. The substrate in accordance with claim 1, wherein a distance between two adjacent openings of the plurality of openings is not less than 0.2 mm.

3. The substrate in accordance with claim 1, wherein the ground/power layer between two adjacent openings of the plurality of openings is in strip shape.

4. The substrate in accordance with claim 1, wherein a plurality of groups of the inner through holes pass through the corresponding openings and are arranged in a radial arrangement.

5. The substrate in accordance with claim 1, wherein the top surface of the first insulating layer includes a chip-attaching region.

6. The substrate in accordance with claim 5, wherein the plurality of openings are radially oriented to the chip-attaching region.

7. The substrate in accordance with claim 5, further comprising a metal ring formed on the top surface of the first insulating layer between the chip-attaching region and the inner fingers.

8. The substrate in accordance with claim 1, further comprising a second insulating layer formed below the bottom surface of the first insulating layer and the ground/power layer located between the first insulating layer and the second insulating layer.

9. The substrate in accordance with claim 8, further comprising another ground/power layer on the a bottom surface of the second insulating layer.