Input/output architecture for integrated circuits with efficient positioning of integrated circuit elements

• US 6,979,908 B1
• Filed: 11/28/2000
• Issued: 12/27/2005
• Est. Priority Date: 01/11/2000
• Status: Active Grant

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: Ko, U-Ming
• Primary Examiner(s): WILLIAMS, ALEXANDER O
• Application Number:
  US09/723,563
• Time in Patent Office: 1,855 Days
• Field of Search: 257/786, 257/784, 257/357, 257/723, 257/777, 257/691, 257/203, 257/725, 257/360, 257/401, 257/205, 257/206, 257/209, 257/382, 257/377, 257/409, 257/173, 257/362, 257405-207, 257/384, 257/635, 257/355, 257/107.111, 257/173.174, 257/356, 257/363
• US Class Current: 257/786
• CPC Class Codes: H01L 27/0203 Particular design considerations for integrated circuits
• CPC Class Codes: H01L 27/0248 for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection

Abstract

A described embodiment of the present invention includes an integrated circuit having a plurality of I/O modules. The I/O modules include a bond pad formed on a substrate. The I/O modules also include an electrostatic discharge device formed in the substrate. The electrostatic discharge device is at least partially formed beneath the bond pad. The I/O module also includes an I/O buffer formed in the substrate. The I/O buffer is connected to the bond pad. The I/O buffer provides communication between the bond pad and circuitry formed in the substrate. The circuitry is positioned substantially adjacent to both the electrostatic discharge device and the I/O buffer.

Claims

1. An integrated circuit having a plurality of I/O modules, comprising:

a semiconductor substrate having an interior core region and a peripheral region;

a bond pad disposed on said substrate in said peripheral region;

an electrostatic discharge device disposed in the substrate, the electrostatic discharge device being at least partially disposed beneath the bond pad;

circuitry disposed in said substrate in said interior core region; and

an I/O buffer disposed in the substrate in said peripheral region and connected to the bond pad for providing communication between the bond pad and said circuitry, said circuitry positioned substantially adjacent to both the electrostatic discharge device and the I/O buffer.

2. The integrated circuit of claim 1 wherein the substrate is a silicon substrate.

3. The integrated circuit of claim 1 wherein the I/O buffer is an output buffer.

4. The integrated circuit of claim 1 wherein the I/O buffer is an input buffer.

5. The integrated circuit of claim 1 wherein the I/O buffer is a complementary output buffer.

6. The integrated circuit of claim 1 wherein the circuitry is CMOS circuitry.

7. The integrated circuit of claim 1 wherein the circuitry is BiCMOS circuitry.

8. The integrated circuit of claim 1 wherein the circuitry is an application specific integrated circuit.

9. The integrated circuit of claim 1 wherein the circuitry is digital signal processor.

10. The integrated circuit of claim 1 wherein the entire surface of the substrate beneath the bond pad is occupied by the electrostatic discharge device.