Descriptor-based load balancing
First Claim
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1. An integrated circuit multiprocessor apparatus for processing a plurality of data packets, comprising:
- a plurality of processors;
an interface circuit for receiving and transmitting a plurality of data packets;
a memory comprising a plurality of descriptors, each of said plurality of descriptors comprising an ownership indication, a start of packet indication, an end of packet indication, a buffer length value and a buffer address for specifying a location of a buffer in memory for storing at least a portion of a data packet;
a packet manager circuit coupled between the interface circuit and the memory to transfer data packets between the interface circuit and memory, wherein the packet manager circuit is configured to transfer a first data packet under control of at least a first descriptor and to transfer a second data packet under control of at least a second descriptor, wherein said packet manager is configured to write back to memory all descriptors associated with a data packet upon completion of the transfer of said data packet and said descriptors are written back in the order in which they are released.
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Abstract
A multiprocessor switching device substantially implemented on a single CMOS integrated circuit is described in connection with a descriptor-based packet processing mechanism for use in efficiently assigning and processing packets to a plurality of processors. A plurality of descriptors associated with each packet transfer are written back to memory in order, divided into subset groups and assigned to processors, where each processor searches the assigned subset for EOP and associated SOP descriptors to process.
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Citations
23 Claims
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1. An integrated circuit multiprocessor apparatus for processing a plurality of data packets, comprising:
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a plurality of processors; an interface circuit for receiving and transmitting a plurality of data packets; a memory comprising a plurality of descriptors, each of said plurality of descriptors comprising an ownership indication, a start of packet indication, an end of packet indication, a buffer length value and a buffer address for specifying a location of a buffer in memory for storing at least a portion of a data packet; a packet manager circuit coupled between the interface circuit and the memory to transfer data packets between the interface circuit and memory, wherein the packet manager circuit is configured to transfer a first data packet under control of at least a first descriptor and to transfer a second data packet under control of at least a second descriptor, wherein said packet manager is configured to write back to memory all descriptors associated with a data packet upon completion of the transfer of said data packet and said descriptors are written back in the order in which they are released. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10)
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11. A system for controlling distribution of a plurality of data packets to a plurality of processors, said system comprising:
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a plurality of consecutive descriptor entries; a DMA controller for reading the plurality of consecutive descriptor entries;
storing data packets in a plurality of buffers, each of the plurality of consecutive descriptor entries specifying a buffer for storing at least a portion of a data packet; and
releasing ownership of the plurality of consecutive descriptor entries in order upon completing storage of a data packet;a plurality of processors, each processor configured to process packets; and an assignment processor for assigning a first group of descriptors from the plurality of consecutive descriptor entries to a first processor and for assigning a second group of descriptors from the plurality of consecutive descriptor entries to a second processor; where each processor in the plurality of processors is configured to spin on the final descriptor in its assigned group of descriptors and to process any packet comprising any EOP descriptors contained with its assigned group of descriptors along with any other descriptors associated with each EOP descriptor. - View Dependent Claims (12, 13, 14, 15, 16)
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17. A method comprising:
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creating and releasing a plurality of descriptors to a packet manager, said plurality of descriptors comprising a first descriptor group and a second descriptor group; assigning a first subset of the plurality of descriptors to a first processor and a second subset of the plurality of descriptors to a second processor; receiving a first packet in an interface circuit and transferring the first packet to at least a first memory buffer under control of the first descriptor group; receiving a second packet in the interface circuit and transferring the second packet to at least a second memory buffer under control of the second descriptor group; releasing the first descriptor group to software by writing the first descriptor group to memory; releasing the second descriptor group to software by writing the second descriptor group to memory; and at each processor, identifying any EOP descriptor in the assigned subset of the plurality of descriptors and processing any descriptor associated with said EOP descriptor. - View Dependent Claims (18, 19, 20, 21, 22, 23)
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Specification