Hardware enforced virtual sequentiality

• US 6,981,110 B1
• Filed: 10/06/2002
• Issued: 12/27/2005
• Est. Priority Date: 10/23/2001
• Status: Active Grant

• Current Assignee: F Poszat Hu LLC (Intellectual Ventures LLC)
• Original Assignee: Stephen Waller Melvin
• Inventors: Melvin, Stephen Waller
• Primary Examiner(s): Elmore, Stephen C.
• Application Number:
  US10/065,340
• Time in Patent Office: 1,178 Days
• Field of Search: 711/154, 711/158, 711/221, 370/394, 712/218, 712/225, 709/216, 709/229
• US Class Current: 711/154
• CPC Class Codes: H04L 49/90 Buffering arrangements
• CPC Class Codes: H04L 49/9094 Arrangements for simultaneous transmit and receive, e.g. simultaneous reading/writing from/to the storage element

Abstract

A mechanism processes memory reads and writes in a packet processor. Each memory access has an associated sequence number and information is maintained allowing the detection of memory conflicts. The mechanism is placed between a processing element and a memory system such that write data is buffered and both reads and writes are recorded. When a memory conflict is detected, based on a strict or alternate ordering model, a restart signal is generated and the entries for the associated sequence number are flushed. When the work associated with a sequence number has completed, a signal is made so that associated write data can be sent to the memory system and the entries for that sequence number can be flushed.

Claims

1. A method of processing memory reads and writes in a packet processor comprising the steps of:

receiving a memory read having a first associated sequence number;

receiving a memory write having a second associated sequence number;

determining if a memory conflict exists between said memory read and said memory write based on a comparison of said first associated sequence number and said second associated sequence number; and

signaling a restart based on said step of determining, utilizing said first associated sequence number.

2. The method of claim 1 wherein said step of receiving a memory read comprises the steps of:

recording a first address and said first associated sequence number in a read table;

searching a write table for an entry with an address matching said first address and a sequence number equal to or less than said first associated sequence number;

if said step of searching succeeds, retrieving data from said write table.

3. The method of claim 2 wherein said step of receiving a memory write comprises the step of:

recording a second address, said second associated sequence number and write data in said write table;

and wherein said step of determining if a memory conflict exists comprises the step of;

searching said read table for an entry with an address matching said second address and a sequence number greater than said second associated sequence number the received memory write.

4. The method of claim 3 further comprising the step of:

receiving a start signal with a third associated sequence number; and

receiving a done signal with a fourth associated sequence number;

wherein a list of active sequence numbers is maintained.

5. The method of claim 4 further comprising the steps of:

sending write data to a memory system upon receipt of said done signal;

flushing the entries in said read table and said write table corresponding to said fourth associated sequence number.