Continuous interleave burst access
First Claim
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1. A memory controller, comprising:
- means to detect a first start address for a first burst output from a memory cell array; and
means to generate an anticipated start address for an anticipated burst output, wherein the anticipated start address is based on the first start address and is in anticipation of a second start address such that, when the anticipated start address corresponds to the second start address, the anticipated burst output follows the first burst output and maintains an active data output stream from the memory cell array for the first burst output associated with the first start address and a second burst output associated with the second start address.
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Abstract
A system is described which uses a burst access memory and a memory controller to anticipate the memory address to be used in future data read operations as requested by a microprocessor. Either the memory controller or the memory device initiates a burst read operation starting at a memory address generated thereby. The microprocessor can, therefore, wait to initiate a data read without suffering a time delay.
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Citations
38 Claims
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1. A memory controller, comprising:
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means to detect a first start address for a first burst output from a memory cell array; and means to generate an anticipated start address for an anticipated burst output, wherein the anticipated start address is based on the first start address and is in anticipation of a second start address such that, when the anticipated start address corresponds to the second start address, the anticipated burst output follows the first burst output and maintains an active data output stream from the memory cell array for the first burst output associated with the first start address and a second burst output associated with the second start address. - View Dependent Claims (2, 3)
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4. A memory controller, comprising:
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means to provide a first burst output from a memory cell array in response to a first start address from a microprocessor; means to provide an anticipated start address in anticipation of a second start address from the microprocessor; and means to initiate an anticipated burst output from the memory cell array in response to the anticipated start address, wherein the anticipated burst output follows the first burst output and maintains an active data output stream from the memory cell array for the first start address and the second start address. - View Dependent Claims (5, 6, 7, 8)
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9. A system, comprising:
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a burst access memory, the burst access memory to provide a first burst read output in response to a first memory address; and an address generator to initiate an anticipated burst read output from the burst access memory beginning with an anticipated memory address; wherein, when the anticipated memory address corresponds to a second start address and the anticipated burst read output corresponds to a second burst read output beginning with the second start address, the second burst read output follows the first burst read output and maintains an active data output stream from the burst access memory for the first start address and the second start address. - View Dependent Claims (10, 11, 12, 13)
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14. A system, comprising:
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a burst access memory; a processor to request a first read operation followed by a second read operation, the processor to provide a first start address to the burst access memory for the first read operation and to provide a second start address to the burst access memory for the second read operation; an address generator to detect the first start address and provide an anticipated start address to the burst access memory in response to the first start address; the burst access memory to output a first burst output in response to the first start address and to output an anticipated burst output in response to the anticipated start address, wherein, when the anticipated start address corresponds to the second start address, the anticipated burst output follows the first burst output and maintains an active data output stream from the burst access memory from the first read operation to the second read operation. - View Dependent Claims (15, 16, 17)
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18. A system, comprising:
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addressable memory cells; a processor to generate a first start address to read the memory cells; and a memory controller to receive the first start address, to output a first data series from the addressable memory cells to the processor in response to receiving the first start address, to generate an anticipated start address in response to receiving the first start address, and to output an anticipated data series from the addressable memory cells such that the anticipated data series follows the first data series to maintain an active data output stream from the addressable memory cells to the processor. - View Dependent Claims (19, 20, 21, 22, 23)
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24. A system, comprising:
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a memory device, including addressable memory cells and control circuitry to provide burst outputs from the addressable memory cells in response to an address; a processor to request a first burst read operation from the addressable memory cells followed by a second burst read operation from the addressable memory cells, the processor to provide a first address to the control circuitry of the memory device for the first burst read operation and to provide a second address to the control circuitry of the memory device for the second burst read operation, the memory device to output a first burst output in response to the first address; and an address generator to provide an anticipated address to the memory device based on the first address such that the memory device outputs an anticipated burst output, wherein when the anticipated address corresponds to the second address, the memory device maintains an active data stream for the first burst read operation and the second burst read operation. - View Dependent Claims (25, 26, 27)
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28. A method for outputting data from a burst access memory, comprising:
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receiving a first read request, including receiving a first start address; in response to receiving the first start address, outputting a first data series from the burst access memory beginning with the first start address, and outputting an anticipated data series from the burst access memory beginning with an anticipated start address such that the anticipated data series follows the first data series and maintains an active data stream from the burst access memory; comparing a second start address to the anticipated start address; interrupting the anticipated data series and outputting a second data series from the burst access memory that corresponds to the second start address when the second start address does not correspond to the anticipated start address, and outputting the anticipated data series as the second data series when the second start address corresponds to the anticipated start address. - View Dependent Claims (29, 30, 31, 32, 33)
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34. A method for outputting data from a burst access memory, comprising:
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receiving a first read request, including receiving a first start address; in response to receiving the first start address, outputting a first data series from the burst access memory beginning with the first start address, and outputting an anticipated data series from the burst access memory beginning with an anticipated start address such that the anticipated data series follows the first data series and maintains an active data stream from the burst access memory; comparing a second start address to the anticipated start address; interrupting the anticipated data series if the second start address is not received before the burst access memory is ready to output a second data series, the second data series corresponding to the second start address and further corresponding to the anticipated data series when the second start address corresponds to the anticipated start address.
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35. A method for outputting data from a burst access memory, comprising:
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receiving a first read request, including receiving a first start address; in response to receiving the first start address, outputting a first data series from the burst access memory beginning with the first start address, and outputting an anticipated data series from the burst access memory beginning with an anticipated start address such that the anticipated data series follows the first data series and maintains an active data stream from the burst access memory; comparing a second start address to the anticipated start address; interrupting the anticipated data series if the second start address is not received before a second data series is ready to be presented to a processor, the second data series corresponding to the second start address and further corresponding to the anticipated data series when the second start address corresponds to the anticipated start address.
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36. A method for performing burst read operations, comprising:
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receiving a first address for a first burst read operation; in response to receiving the first address, providing a first burst output from a memory array corresponding to the first burst read operation, generating an anticipated address, and providing an anticipated burst output from the memory array following the first burst output, wherein an active data stream is maintained between the first burst output and the anticipated burst output; comparing a second address corresponding to a second burst read operation to the anticipated address, and when the second address corresponds to the anticipated address, continuing the anticipated burst output as a second burst output from the memory array corresponding to the second burst read operation, wherein an active data stream is maintained from the first and second burst read operations. - View Dependent Claims (37, 38)
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Specification