Redundant memory sequence and fault isolation

• US 6,981,173 B2
• Filed: 09/28/2001
• Issued: 12/27/2005
• Est. Priority Date: 09/28/2001
• Status: Expired due to Term

• Current Assignee: Hewlett-Packard Development Company, L.P. (HP Inc.)
• Original Assignee: Hewlett-Packard Development Company, L.P. (HP Inc.)
• Inventors: Scheffler, Robert A., Ferguson, Patrick L.
• Primary Examiner(s): Beausoliel, Robert
• Assistant Examiner(s): Duncan, Marc M.
• Application Number:
  US09/965,877
• Publication Number:
  US 20030070113A1
• Time in Patent Office: 1,551 Days
• Field of Search: 714/5, 714/7, 711/115, 710/302
• US Class Current: 714/5.11
• CPC Class Codes: H04L 1/22 using redundant apparatus to increase reliability

Abstract

A computer system includes a plurality of memory modules that contain semiconductor memory, such as DIMMs. The system includes a host/data controller that utilizes an XOR engine to store data and parity information in a striped fashion across on a plurality of memory cartridges each containing a plurality of memory modules to create a redundant array of industry standard DIMMs (RAID). Each memory cartridge includes an independent memory controller and a corresponding control mechanism in the host/data controller to interpret the independent transitioning of each memory cartridge between various states, including a redundant-ready and a powerdown state to facilitate “hot-plug” capabilities utilizing the removable memory cartridges. Fault information may be passed between the individual memory controllers and the host/data controller to facilitate expedient fault isolation.

Claims

1. A computer system comprising:

a memory system comprising a plurality of memory cartridges, each of the plurality of memory cartridges comprising at least one memory device and a memory controller; and

a data controller comprising a plurality of control mechanisms, each of the plurality of control mechanisms corresponding to a respective one of the memory controllers and configured to independently interpret the transition of the corresponding memory cartridge between a first state of operation and a second state of operation, wherein the first state of operation permits the memory cartridge to be used to store data in a redundant memory array and wherein the second state of operation prevents the memory cartridge from being used to store data in a redundant memory array, and wherein the second state of operation comprises one of a disable-up state, a disable-down state, a powerup state, a powerdown state, and a verify/replace state of operation.

2. The computer system, as set forth in claim 1, wherein the at least one memory device comprises a dual inline memory module (DIMM).

3. The computer system, as set forth in claim 1, wherein the first state of operation comprises a redundant-ready state of operation.

4. The computer system, as set forth in claim 1, wherein the memory system is configured to operate in a redundant mode when each of the plurality of memory cartridges is in the redundant-ready state.

5. The computer system, as set forth in claim 1, wherein the plurality of memory cartridges comprises five memory cartridges.

6. The computer system, as set forth in claim 1, wherein at least one of the plurality of memory cartridges is configured to store parity data.

7. The computer system, as set forth in claim 1, wherein each memory controller is configured to control access to the at least one memory device on the corresponding memory cartridge.

8. The computer system, as set forth in claim 1, wherein the data controller writes data in a striped fashion across the plurality of memory cartridges.

9. The computer system, as set forth in claim 1, wherein each of the plurality of control mechanisms is configured to independently facilitate the transition of the corresponding memory cartridge to one of a redundant-ready state, a powerdown state, a powerup state, a disable-down state, a disable-up state, and a verify/replace state.

10. A method of hot-plugging a memory cartridge comprising the acts of:

(a) operating the memory cartridge in a redundant-ready state;

(b) transitioning the memory cartridge from the redundant-ready state to a disable-down state to facilitate a de-assertion sequence of control signals;

(c) transitioning the memory cartridge from the disable-down state to a powerdown state wherein power is de-asserted to the memory cartridge;

(d) replacing at least a portion of the memory cartridge;

(e) transitioning the memory cartridge from the powerdown state to a powerup state wherein power is asserted to the memory cartridge;

(f) transitioning the memory cartridge from the powerup state to a disable-up state to facilitate an assertion sequence of control signals;

(g) transitioning the memory cartridge from the disable-up state to a verify/replace state to verify the proper functionality of the memory cartridge and to replace data stored in the memory cartridge with valid system data; and

(h) transitioning the memory cartridge from the verify/replace state to the redundant-ready state.

11. The method, as set forth in claim 10, wherein act (a) comprises the act of utilizing error correction code to correct errors to prevent the occurrence of a fault.

12. The method, as set forth in claim 10, wherein act (c) comprises the act of driving all write interface outputs and all read interface inputs to a logical zero.

13. The method, as set forth in claim 10, wherein act (d) comprises the act of replacing at least one memory device on the memory cartridge.

14. The method, as set forth in claim 10, wherein act (d) comprises the act of replacing the memory cartridge with a different memory cartridge.

15. The method, as set forth in claim 10, wherein act (e) comprises the act of driving all write interfaces to an idle state and all read interface inputs to a tristate condition.

16. The method, as set forth in claim 10, wherein act (g) comprises the acts of:

writing data to the memory cartridge; and

reading the data from the memory cartridge.

17. The method of claim 16, wherein the acts are performed in the recited order.

18. A of operating a memory system in a redundant mode, the memory system comprising a plurality of memory cartridges, comprising the act of independently transitioning each of the plurality of memory cartridges to a redundant-ready state, wherein the act of independently transitioning each of the plurality of memory cartridges to a redundant-ready state, comprises the act of independently transitioning each of the plurality of memory cartridges to a redundant-ready state from a disable-down state.

19. A of operating a memory system in a redundant mode, the memory system comprising a plurality of memory cartridges, comprising the act of independently transitioning each of the plurality of memory cartridges to a redundant-ready state, wherein the act of independently transitioning each of the plurality of memory cartridges to a redundant-ready state, comprises the act of independently transitioning each of the plurality of memory cartridges to a redundant-ready state from a disable-up state.

20. A of operating a memory system in a redundant mode, the memory system comprising a plurality of memory cartridges, comprising the act of independently transitioning each of the plurality of memory cartridges to a redundant-ready state, wherein the act of independently transitioning each of the plurality of memory cartridges to a redundant-ready state, comprises the act of independently transitioning each of the plurality of memory cartridges to a redundant-ready state from a verify/replace state.