Structure and fabricating method with self-aligned bit line contact to word line in split gate flash

• US 6,982,201 B2
• Filed: 10/13/2004
• Issued: 01/03/2006
• Est. Priority Date: 08/20/2002
• Status: Expired due to Fees

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Hsieh, Chia Ta
• Primary Examiner(s): SARKAR, ASOK K
• Application Number:
  US10/964,391
• Publication Number:
  US 20050048721A1
• Time in Patent Office: 447 Days
• Field of Search: 438/201, 438/211, 438/257, 438/264, 438/266, 438/267, 438/304, 438593-596
• US Class Current: 438/257
• CPC Class Codes: H01L 21/76897 Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step self-aligned silicidation on field effect transistors H01L29/665
• CPC Class Codes: H10B 41/30 characterised by the memory core region
• CPC Class Codes: H10B 69/00 Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices

Abstract

A new structure is disclosed for semiconductor devices in which contact regions are self-aligned to conductive lines. Openings to a gate oxide layer, in partially fabricated devices on a silicon substrate, have insulating sidewalls. First polysilicon lines disposed against the insulating sidewalls extend from below the top of the openings to the gate oxide layer. Oxide layers are grown over the top and exposed sides of the first polysilicon lines serving to insulate the first polysilicon lines. Polysilicon contact regions are disposed directly over and connect to silicon substrate regions through openings in the gate oxide layer and fill the available volume of the openings. Second polysilicon lines connect to the contact regions and are disposed over the oxide layers grown on the first polysilicon lines.

Claims

1. A method of forming a structure for split gate flash memory comprising:

providing a semiconductor substrate comprising split gate structures and drain surfaces, where a first insulator layer is formed over the split gate structures;

forming doped polysilicon spacer regions between the split gate structures and the drain surfaces;

oxidizing the drain surfaces to form a second insulator layer and oxidizing surfaces of the doped polysilicon spacer regions to form a third insulator layer, wherein the thickness of the second insulator layer is thinner than the third insulator layer;

removing the second insulator layer over the drain surfaces;

implanting ions into the drain surfaces to form drain regions; and

forming a conductive layer over the drain regions.

2. A method of forming a structure for split gate flash memory comprising:

providing a semiconductor substrate;

forming split gate structures over the semiconductor substrate;

conformably forming a first insulator layer over the split gate structures and the semiconductor substrate;

forming conductive spacer regions over the first insulator layer;

etching the first insulator layer to expose drain surfaces of the semiconductor substrate;

forming a second insulator layer over the drain surfaces and a third insulator layer over the conductive spacer regions, wherein the thickness of the second insulator layer is thinner than the third insulator layer;

removing the second insulator layer over the drain surfaces;

implanting ions into the drain surfaces to form drain regions; and

forming a conductive layer over the drain regions.

3. A method of forming a structure for split gate flash memory comprising:

providing a semiconductor substrate;

forming split gate structures over the semiconductor substrate;

conformably forming a first insulator layer over the split gate structures and the semiconductor substrate;

forming a first conductive layer over the first insulator layer;

planarizing the first conductive layer to the top of the first insulating layer;

etching the first conductive layer to form square conductive spacer regions against sidewalls of the split gate structures that serve as word lines;

etching the first insulator layer to expose drain surfaces of the semiconductor substrate;

forming a second insulator layer over the drain surfaces and a third insulator layer over the square conductive spacer regions;

removing the second insulator layer over the drain surfaces;

forming drain regions in the drain surfaces; and

forming a second conductive layer over the drain regions that serve as bit lines.