Digital logic devices with extremely skewed trip points and reset circuitry for rapidly propagating signal edges, circuits and systems including same

• US 6,982,572 B2
• Filed: 01/03/2003
• Issued: 01/03/2006
• Est. Priority Date: 08/03/2001
• Status: Expired due to Fees

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Weber, Larren G., Gans, Dean D., Porter, John D.
• Primary Examiner(s): Tokar, Michael
• Assistant Examiner(s): Mai, Lam T.
• Application Number:
  US10/336,356
• Publication Number:
  US 20030098713A1
• Time in Patent Office: 1,096 Days
• Field of Search: 326/82, 326/83, 326/26, 326/27, 326/112
• US Class Current: 326/82
• CPC Class Codes: H03K 19/01721 by means of a pull-up or down element

Abstract

The invention includes digital logic devices with extremely skewed trip points and reset circuitry for rapidly propagating signal edges. Embodiments of skewed logic devices in accordance with the present invention include inverters, buffers, NOR gates and NAND gates for rapidly propagating a selected “fast” edge of an input signal. Additional embodiments include pulse stretchers, memory devices, substrates, computer systems and methods incorporating the skewed logic devices of the present invention. Each embodiment of a skewed logic device of the present invention is configured to propagate either a fast rising edge or fast falling edge of an output signal, i.e., the “fast” edge, at rates comparable to those of domino logic. An advantage of the skewed logic devices of the present invention over conventional CMOS logic devices is rapid edge propagation. Additionally, virtually all of the input gate loading is devoted to the fast edge being propagated. Additionally, the reset networks, as disclosed herein, are buffered by at least two gates, thus reducing loading seen by the input or the output of the skewed logic device.

Claims

1. A skewed buffer rising logic device for rapidly propagating a rising edge of an output signal comprising:

a fast inverter falling having a large n/p channel width ratio for receiving a rising edge of an input signal and rapidly propagating a falling edge of an intermediate signal in response thereto;

a fast inverter rising having a large p/n channel width ratio and in series with said fast inverter falling for receiving said rapidly propagated falling edge of said intermediate signal and rapidly propagated rising edge of said output signal;

a reset network coupled to said fast inverter falling and said fast inverter rising for resetting output signals of said fast inverter falling and said fast inverter rising after said rising edge of said output signal has been rapidly propagated; and

a feedback delay circuit operably coupled between an output of said fast inverter rising and an input of said reset network for propagating said output signal to said reset network.

2. The skewed buffer rising logic device of claim 1, wherein said large n/p channel width ratio ranges from about 5 to about 200.

3. The skewed buffer rising logic device of claim 1, wherein said large p/n channel width ratio ranges from about 5 to about 200.

4. The skewed buffer rising logic device of claim 1, wherein said reset network comprises:

combinational logic for receiving said input signal;

a big PMOS pull-up transistor having a wide p-channel at least 10 μ

m across, a gate node driven by an output of said combinational logic, a source node connected to a supply voltage and a drain node coupled to said intermediate signal for pulling said intermediate signal up to said supply voltage in response to a low signal on said gate node;

an inverter having input connected to said gate node of said big PMOS pull-up transistor; and

a big NMOS pull-down transistor having a wide n-channel at least 10 μ

m across, a gate node connected to an output of said inverter, a drain node connected to said output signal and a source node connected to ground potential.

5. The skewed buffer rising logic device of claim 4, wherein said combinational logic performs a logical OR function.

6. The skewed buffer rising logic device of claim 4, wherein said combinational logic comprises:

a NOR gate with a first input connected to said input signal and a second input connected to an output of said feedback delay circuit; and

a second inverter having an input connected to an output of said NOR gate and having an output connected to said gate node of said big PMOS pull-up transistor.

7. The skewed buffer rising logic device of claim 3, wherein said feedback delay circuit comprises five inverters connected in series.