Method and apparatus for reading NAND flash memory array

• US 6,982,905 B2
• Filed: 10/09/2003
• Issued: 01/03/2006
• Est. Priority Date: 10/09/2003
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Nguyen, Dzung H.
• Primary Examiner(s): Hoang, Huan
• Application Number:
  US10/682,585
• Publication Number:
  US 20050078518A1
• Time in Patent Office: 817 Days
• Field of Search: 365/185.17, 365/185.18, 365/185.22
• US Class Current: 365/185.17
• CPC Class Codes: G11C 16/26 Sensing or reading circuits; Data output circuits

Abstract

The method for reading/verifying a NAND flash memory device alternates the select gate biasing in response to the position of the cell to be read. If the cell is closer to the top of the column, the SG(D) line is biased prior to the SG(S) line. If the cell is closer to the bottom of the column, the SG(S) line is biased prior to the SG(D) line.

Claims

1. A method for reading/verifying a NAND flash memory array comprising a column of memory cells having a first end controlled by a select gate drain line and a second end controlled by a select gate source line, the method comprising:

decoding an input address signal to determine which cell to select; and

biasing the select gate drain and select gate source lines in an order responsive to a position of the selected cell in the column.

2. The method of claim 1 wherein the select gate drain and source lines are biased at a voltage substantially equal to 4.5V.

3. The method of claim 1 wherein if the selected cell is at the first end, biasing the select gate drain line prior to biasing the select gate source line.

4. The method of claim 1 wherein if the position of the selected cell is within three cells of the first end, biasing the select gate drain line prior to biasing the select gate source line.

5. A method for reading/verifying a NAND flash memory array comprising a column of series coupled memory cells having a drain end controlled by a select gate drain line and a source end controlled by a select gate source line, each cell controlled by a wordline, the method comprising:

decoding an input address signal to determine which cell to select;

if the selected cell is within a predetermined range of the drain end of the column, biasing the select gate drain line prior to biasing the select gate source line; and

if the selected cell is within a predetermined range of the source end of the column, biasing the select gate source line prior to biasing the select gate drain line.

6. The method of claim 5 and further including:

biasing the wordlines of the unselected cells of the column at a voltage substantially equal to 4.5V; and

biasing the wordline of the selected cell at a voltage substantially equal to 0V.

7. A method for reading/verifying a NAND flash memory array comprising a column of series coupled memory cells having a drain end controlled by a select gate drain line and a source end controlled by a select gate source line, each cell controlled by a wordline, the method comprising:

decoding an input address signal to determine which cell to select;

if the selected cell is the first cell at the drain end of the column, biasing the select gate drain line prior to biasing the select gate source line;

if the selected cell is the last cell at the source end of the column, biasing the select gate source line prior to biasing the select gate drain line;

biasing the unselected wordlines at a first predetermined voltage; and

biasing the selected wordline at a second predetermined voltage.

8. The method of claim 7 wherein the first predetermined voltage is substantially equal to 4.5V and the second predetermined voltage is equal to 0V.

9. A NAND flash memory device comprising:

a NAND memory array having columns of cells coupled in series, each cell selected by a wordline;

a select gate source line coupled to a source control transistor at a source end of the column of cells; and

a select gate drain line coupled to a drain control transistor at a drain end of the column of cells, the select gate drain line capable of turning on the drain control transistor prior to the source control transistor when a selected cell is within a predetermined number of cells of the drain control transistor.

10. The memory device of claim 9 and further including a bit line coupled to the drain control transistor and a source line coupled to the source control transistor.

11. A NAND flash memory device comprising:

biasing wordlines to unselected cells in the column at a voltage substantially equal to 4.5V and a wordline to the selected cell at a voltage substantially equal to 0V.

12. The memory device of claim 11 and further including:

a bitline coupled to the drain control transistor; and

a source line coupled to the source control transistor.

13. The memory device of claim 11 wherein the source control transistor and the drain control transistor are turned on by a bias voltage.

14. A flash memory device comprising:

an address decoder that decodes an input address;

a NAND memory array coupled to the address decoder, the array having columns of cells coupled in series, each cell controlled by a wordline selected by the address decoder;

a select gate drain line coupled to a drain control transistor at a drain end of the column of cells, the select gate drain line having a bias voltage prior to a select gate source line if a selected cell is within a predetermined range of the drain control transistor; and

the select gate source line coupled to a source control transistor at a source end of the column of cells, the select gate source line having a bias prior to the select gate drain line if the selected cell is within a predetermined range of the source control transistor,

biasing wordlines to unselected cells in the column at a voltage substantially equal to 4.5V and a wordline to the selected cell at a voltage substantilly equal to 0V.

15. The memory device of claim 14 wherein the address decoder comprises a row decoder and a column decoder.

16. The memory device of claim 14 wherein the select gate drain line is capacitively coupled to the wordline of the selected cell.

17. The memory device of claim 14 wherein the select gate source line is capacitively coupled to the wordline of the selected cell.

18. An electronic system comprising:

a processor that generates an address bus; and

a NAND flash memory device coupled to the processor, the memory device comprising;

an address decoder that decodes an address from the address bus;

a NAND memory array coupled to the address decoder, the array having columns of cells coupled in series, each cell controlled by a wordline selected by the address decoder;

a select gate drain line coupled to a drain control transistor at a drain end of the column of cells, the select gate drain line having a bias voltage prior to a select gate source line if a selected cell is within a predetermined range of the drain control transistor; and

the select gate source line coupled to a source control transistor at a source end of the column of cells, the select gate source line having a bias prior to the select gate drain line if the selected cell is within a predetermined range of the source control transistor.

19. The electronic system of claim 18 wherein the predetermine range is one cell.

20. A method for reading/verifying a NAND flash memory array comprising a column of memory cells having a first end controlled by a select gate drain line and a second end controlled by a select gate source line, the method comprising:

decoding an input address signal to determine which cell to select;

biasing the select gate drain and select gate source lines in an order responsive to a position of the selected cell in the column; and

a NAND memory array having columns of cells coupled in series, each cell selected by a wordline;

a select gate source line coupled to a source control transistor at a source end of the column of cells, the select gate source line capable of turning on the source control transistor prior to a drain control transistor when a selected cell is within a predetermined number of cells of the source control transistor; and

a select gate drain line coupled to a drain control transistor at a drain end of the column of cells, the select gate drain line capable of turning on the drain control transistor prior to the source control transistor when the selected cell is within a predetermined number of cells of the drain control transistor.