Data read circuit for use in a semiconductor memory and a memory thereof
First Claim
1. A data read circuit for use in a semiconductor memory device having a memory cell array, the memory cell array having a plurality of unit cells, the data read circuit comprising:
- a selector for selecting one of the plurality of unit cells in response to an address signal;
a clamping unit connected between a bit line coupled with the selected unit cell and a sensing node, the clamping unit for supplying a clamp voltage having a level for a read operation to the bit line of the selected unit cell in response to a clamp control signal;
a precharge unit for precharging the sensing node to a voltage having a power source level in response to a control signal of a first state applied during a precharge mode, and compensating through the sensing node for a reduced quantity of current at the bit line connected to the selected unit cell in response to a control signal of a second state applied during a data sensing mode; and
a sense amplifier unit for comparing a level of the sensing node with a reference level and for sensing data stored in the selected unit cell, when the control signal of the second state is applied to the precharge unit.
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Abstract
A data read circuit and method for use in a semiconductor memory device that has a memory cell array are provided. The circuit includes a selector for selecting a unit cell within the memory cell array in response to an address signal; a clamping unit for supplying a clamp voltage having a level for a read operation to a bit line of the selected unit cell in response to a clamp control signal; a precharge unit for precharging a sensing node to a voltage having a power source level in response to a control signal of a first state in a precharge mode, and compensating through the sensing node for a reduced quantity of current at the bit line in response to a control signal of a second state in a data sensing mode; and a sense amplifier unit for comparing a level of the sensing node with a reference level, and for sensing data stored in the selected unit cell.
73 Citations
20 Claims
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1. A data read circuit for use in a semiconductor memory device having a memory cell array, the memory cell array having a plurality of unit cells, the data read circuit comprising:
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a selector for selecting one of the plurality of unit cells in response to an address signal; a clamping unit connected between a bit line coupled with the selected unit cell and a sensing node, the clamping unit for supplying a clamp voltage having a level for a read operation to the bit line of the selected unit cell in response to a clamp control signal; a precharge unit for precharging the sensing node to a voltage having a power source level in response to a control signal of a first state applied during a precharge mode, and compensating through the sensing node for a reduced quantity of current at the bit line connected to the selected unit cell in response to a control signal of a second state applied during a data sensing mode; and a sense amplifier unit for comparing a level of the sensing node with a reference level and for sensing data stored in the selected unit cell, when the control signal of the second state is applied to the precharge unit. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14)
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15. A method of controlling a data sensing node in a semiconductor memory device, the semiconductor memory device having a memory cell array comprising a plurality of unit cells each of the plurality of unit cells having an access transistor and a variable resistor;
- a sense amplifier for sensing data stored in the plurality of unit cells; and
a transistor connected between a sensing node of the sense amplifier and a power source, the method comprising;operating the transistor connected between the sensing node of the sense amplifier and the power source under a turn-on state without entering a turn-off state when in a precharge mode and a data sensing mode; and receiving the power source supplied from the transistor at the sensing node. - View Dependent Claims (16, 17)
- a sense amplifier for sensing data stored in the plurality of unit cells; and
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18. A method of reading data in a semiconductor memory device having a memory cell array having a plurality of unit cells, the method comprising:
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precharging a sensing node to a power source level in response to a control signal of a first state; selecting a unit cell from the memory cell array in response to an address signal; clamping a level of a bit line of the selected unit cell at a clamp level in response to a clamp control signal applied simultaneously upon completion of the precharging, and supplying a bias current to the sensing node in response to a control signal of a second state applied simultaneously upon completion of the precharing, to compensate for a reduced quantity of current at the bit line connected to the selected unit cell; and sensing and outputting data of the selected unit cell by comparing a level of the sensing node with a reference level. - View Dependent Claims (19, 20)
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Specification