Virtual loop carrier system with network clock recovery

• US 6,982,993 B1
• Filed: 11/28/2000
• Issued: 01/03/2006
• Est. Priority Date: 11/17/1998
• Status: Active Grant

• Current Assignee: Cisco Technology, Inc. (Cisco Systems, Inc.)
• Original Assignee: Cisco Technology, Inc. (Cisco Systems, Inc.)
• Inventors: Narayan, Sriram, Claveloux, Denis
• Primary Examiner(s): Kizou, Hassan
• Assistant Examiner(s): Levitan, Dmitry
• Application Number:
  US09/724,303
• Time in Patent Office: 1,862 Days
• Field of Search: 370/464, 370/498, 370503-520, 455/75, 455/76
• US Class Current: 370/503
• CPC Class Codes: H04L 12/66 Arrangements for connecting between networks having differing types of switching systems, e.g. gateways

Abstract

A loop carrier system includes a home local area network having plural telephone modules and a hub coupled to in-home telephone wiring. The telephone modules and the hub communicate voice signals over the in-home wiring in a dedicated frequency band above baseband POTS. The hub converts between voice signals and voice packets and is connected to a network access device for transferring the voice packets from the home local area network to a telecommunications network which routes the voice packets to a gateway. The gateway converts between the voice packets and a circuit format compatible with a local digital voice switch. The home local area network includes a timing recovery mechanism which in the absence of a clock that is traceable to the Primary Reference Clock on the public network is robust to clock drift, cell delay variation and cell impairments.

Claims

1. A method of providing clock timing in a receiver, the method comprising:

providing a local clock signal having a reference frequency by dividing a local oscillator signal by a clock divisor having an initial nominal value;

receiving a stream of data cells in a receiver buffer;

servicing the receiver buffer to remove the data cells at a servicing rate based on the local clock signal;

monitoring fullness of the receiver buffer at a monitoring interval;

upon buffer fullness exceeding a high buffer threshold, adjusting the clock reference frequency upwards by setting the clock divisor to a value less than the nominal value and by stretching the local clock signal by half a cycle of the local oscillator signal;

upon buffer fullness dropping below a low buffer threshold, adjusting the clock reference frequency downwards by setting the clock divisor to the nominal value and by stretching the local clock signal by half a cycle of the local oscillator signal.

2. The method of claim 1 further comprising:

once the buffer fullness exceeds the high buffer threshold and upon buffer fullness dropping below a nominal threshold less than the high buffer threshold and greater than the low buffer threshold, adjusting the clock reference frequency downwards by setting the clock divisor to the nominal value without stretching the local clock signal by half a cycle of the local oscillator signal.

3. The method of claim 1 further comprising:

once the buffer fullness drops below the low buffer threshold and upon buffer fullness exceeding a nominal threshold less than the high buffer threshold and greater than the low buffer threshold, adjusting the clock reference frequency upwards by setting the clock divisor to the nominal value without stretching the local clock signal by half a cycle of the local oscillator signal.

4. The method of claim 1 wherein the cell stream is an AAL1 stream and wherein the monitoring interval comprises a first number of ATM cell periods.

5. The method of claim 4 wherein clock adjustment is made only if buffer fullness exceeds the high buffer threshold or drops below the low buffer threshold at each monitoring interval for a second number of consecutive monitoring intervals.

6. The method of claim 1 wherein the cell stream includes cells from plural virtual circuits and receiving includes receiving cells from the plural virtual circuits in respective receiver buffers.

7. The method of claim 6 further comprising selecting one of the plural virtual circuits and wherein monitoring includes monitoring fullness of the receiver buffer corresponding to the selected virtual circuit.

8. A receiver comprising:

a clock source for providing a local clock signal having a reference frequency by dividing a local oscillator signal by a clock divisor having an initial nominal value;

a receiver buffer for receiving a stream of data cells;

means for servicing the receiver buffer to remove the data cells at a servicing rate based on the local clock signal;

means for monitoring fullness of the receiver buffer at a monitoring interval;

means for adjusting the clock reference frequency upwards upon buffer fullness exceeding a high buffer threshold by setting the clock divisor to a value less than the nominal value and by stretching the local clock signal by half a cycle of the local oscillator signal and for adjusting the clock reference frequency downwards upon buffer fullness dropping below a low buffer threshold by setting the clock divisor to the nominal value and by stretching the local clock signal by half a cycle of the local oscillator signal.

9. The receiver of claim 8 wherein the cell stream is an AAL1 stream and wherein the monitoring interval comprises a first number of ATM cell periods.

10. The receiver of claim 9 wherein clock adjustment is made only if buffer fullness exceeds the high buffer threshold or drops below the low buffer threshold at each monitoring interval for a second number of consecutive monitoring intervals.

11. The receiver of claim 8 wherein the receiver buffer comprises plural receiver buffers and wherein the cell stream includes cells from plural virtual circuits and the plural receiver buffers receive cells from respective virtual circuits.

12. The receiver of claim 11 further comprising means for selecting one of the plural virtual circuits and wherein monitoring includes monitoring fullness of the receiver buffer corresponding to the selected virtual circuit.