Graphical program having a timing specification and method for conversion into a hardware implementation

• US 6,983,228 B2
• Filed: 05/09/2003
• Issued: 01/03/2006
• Est. Priority Date: 08/18/1997
• Status: Expired due to Fees

• Current Assignee: National Instruments Corporation (Emerson Electric Company)
• Original Assignee: National Instruments Corporation (Emerson Electric Company)
• Inventors: Kodosky, Jeffrey L., Butler, Cary P., Odom, Brian K., Andrade, Hugo
• Primary Examiner(s): Frejd, Russell
• Application Number:
  US10/434,950
• Publication Number:
  US 20030195730A1
• Time in Patent Office: 970 Days
• Field of Search: 703/2, 703/22, 702/119, 702/119.57, 702/123, 702/127, 716/1, 716 16- 18, 717/106, 717/125, 345/700, 345/771
• US Class Current: 703/2
• CPC Class Codes: G06F 11/2294 by remote test
• CPC Class Codes: G06F 11/2733 Test interface between tester and unit under test
• CPC Class Codes: G06F 2111/12 Symbolic schematics
• CPC Class Codes: G06F 30/34 for reconfigurable circuits, e.g. field programmable gate arrays [FPGA] or programmable logic devices [PLD]
• CPC Class Codes: G06F 8/34 Graphical or visual programming

Abstract

A computer-implemented system and method for generating a hardware implementation of graphical code. The method comprises first creating a graphical program. A first portion of the graphical program may optionally be compiled into machine code for execution by a CPU. A second portion of the graphical program is converted into a hardware implementation according to the present invention. The operation of converting the graphical program into a hardware implementation comprises exporting the second portion of the graphical program into a hardware description, wherein the hardware description describes a hardware implementation of the second portion of the graphical program, and then configuring a programmable hardware element utilizing the hardware description to produce a configured hardware element. The configured hardware element thus implements a hardware implementation of the second portion of the graphical program.

Claims

1. A memory medium which stores program instructions for configuring a device, wherein the device includes a programmable hardware element, wherein the program instructions are executable by a processor to perform:

storing a block diagram, wherein the block diagram specifies a function, wherein the block diagram comprises a timing specification visually depicted in the block diagram specifying timing information of the block diagram;

generating a hardware description based on the block diagram, wherein the hardware description describes a hardware implementation of the block diagram, wherein the hardware description incorporates the timing specification; and

configuring the programmable hardware element in the device utilizing the hardware description to produce a configured hardware element, wherein the configured hardware element implements a hardware implementation of the block diagram, wherein the configured hardware element is operable to perform the function according to the timing specification.

2. The memory medium of claim 1,

wherein the timing specification is iconically depicted in the block diagram.

3. The memory medium of claim 1, wherein the timing specification visually depicted in the block diagram comprises a timing icon.

4. The memory medium of claim 1,

wherein the block diagram comprises one or more function nodes;

and

wherein the timing specification specifies one or more of period and phase for iterative execution of the one or more function nodes.

5. The memory medium of claim 1,

wherein the block diagram comprises a plurality of function nodes;

and

wherein the timing specification specifies timing for one or more of the plurality of function nodes.

6. The memory medium of claim 1,

wherein the block diagram comprises a plurality of function nodes connected by lines, wherein the lines indicate that data produced by one function node is used by another function node;

wherein the block diagram also comprises a structure node, wherein the structure node controls execution of one or more of the function nodes; and

wherein the timing specification is associated with the structure node, and specifies timing information of the structure node for controlling execution of the one or more function nodes.

7. The memory medium of claim 6,

wherein the structure node comprises a while loop;

wherein the while loop operates to control iterative execution of the one or more function nodes; and

wherein the timing specification specifies one or more of period and phase for the while loop.

8. The memory medium of claim 7,

wherein the timing specification comprises input terminals included on the while loop configured to receive one or more of period and phase for the while loop.

9. The memory medium of claim 1,

wherein said generating includes incorporating a register in the hardware description for the block diagram;

and

wherein the configured hardware element in the device is operable to access the register on the configured hardware element to perform the function in accordance with the timing specification.

10. The memory medium of claim 1,

wherein the block diagram includes a looping element which specifies looping of at least a portion of the block diagram;

and

wherein the timing specification specifies timing information for the looping.

11. The memory medium of claim 10,

wherein the timing specification specifies one or more of period and phase of the looping with respect to one or more other loops in the block diagram.

12. The memory medium of claim 11,

wherein the block diagram is associated with one or more panels, wherein the one or more panels are operable to be displayed on a display of a computer system while the device performs the function, and wherein each of the one or more panels is operable to receive user input for providing input to the configured hardware element during said performing, and/or display data generated by the device during said performing.

13. The memory medium of claim 12,

wherein the device is operable to couple to a computer system, wherein the computer system includes the display;

and

wherein the computer system is operable to execute software to display the one or more panels on the display while the configured hardware element in the device executes to perform the function.

14. The memory medium of claim 13, wherein the block diagram and the one or more panels compose a graphical program, and wherein the program instructions are further executable by a processor to perform:

compiling a portion of the graphical program corresponding to the one or more panels into executable code for execution by the computer system.

15. The memory medium of claim 12,

wherein said generating includes incorporating a register in the hardware description for at least one of the one or more panels;

and

wherein the configured hardware element in the device is operable to perform the function by accessing a register on the configured hardware element to affect values displayed in one of said one or more panels.

16. The memory medium of claim 10,

wherein the at least a portion of the block diagram is comprised within an interior portion of the looping element.

17. The memory medium of claim 16, wherein the configured hardware element in the device is executable to perform one or more of:

a measurement function;

a process control function;

an automation function;

an instrumentation function;

a testing function; and

a process modeling function.

18. The memory medium of claim 1, wherein the program instructions are further executable by a processor to perform:

converting the hardware description into a net list, wherein the netlist incorporates the timing specification; and

compiling the net list format into a hardware program file, wherein the hardware program file incorporates the timing specification;

wherein said configuring the programmable hardware element includes downloading the hardware program file to the programmable hardware element to configure the programmable hardware element.

19. The memory medium of claim 18, wherein said converting the hardware description into a net list includes:

utilizing at least one function block from a library of pre-compiled function blocks; and

utilizing hardware target specific information.

20. The memory medium of claim 1,

wherein the block diagram has associated data structures which represent the block diagram, and wherein at least one of the data structures represents the timing specification;

and

wherein said generating the hardware description comprises;

traversing the data structures;

converting the data structures into a hardware description format in response to said traversing.

21. The memory medium of claim 1,

wherein the block diagram includes a plurality of nodes, including a timing specification node comprising the timing specification;

and

wherein said generating the hardware description comprises converting each of said nodes into a hardware description format.

22. The memory medium of claim 21, wherein the block diagram includes a structure node indicating a control function, and wherein the timing specification specifies timing information for the structure node;

wherein, for said structure node, said converting comprises;

determining inputs and outputs to/from the structure node;

generating a hardware description of a control block which performs the control function indicated by the structure node in accordance with the timing specification; and

traversing input dependencies of the node.

23. The memory medium of claim 1, wherein the program instructions are further executable by a processor to perform;

compiling a first portion of the block diagram portion into machine code for execution by a computer system coupled to the device;

wherein a second portion of the block diagram portion is converted into a hardware description;

wherein the configured hardware element is operable to perform functionality indicated by the second portion of the block diagram portion in accordance with the timing specification;

wherein the machine code is executable to perform functionality indicated by the first portion of the block diagram portion; and

wherein said executing the machine code and the configured hardware element performing functionality operate to perform functionality indicated by the block diagram.

24. The memory medium of claim 1, wherein the device includes a non-volatile memory coupled to the programmable hardware element, wherein the program instructions are further executable by the processor to perform:

storing the hardware description into the non-volatile memory;

wherein said configuring the programmable hardware element comprises transferring the hardware description from the non-volatile memory to the programmable hardware element to produce the configured hardware element.

25. The memory medium of claim 1, wherein the block diagram is a data flow diagram.

26. The memory medium of claim 1, wherein the block diagram comprises a plurality of interconnected icons which visually indicate functionality of the block diagram.

27. A computer-implemented method for configuring a device, wherein the device includes a programmable hardware element, the method comprising:

creating a block diagram, wherein the block diagram specifies a function, wherein the block diagram includes a timing specification visually depicted in the block diagram;

generating a hardware description based on the block diagram, wherein the hardware description describes a hardware implementation of the block diagram, wherein the hardware description incorporates the timing specification; and

configuring the programmable hardware element in the device utilizing the hardware description to produce a configured hardware element, wherein the configured hardware element implements a hardware implementation of the block diagram, wherein the configured hardware element is configured to operate according to the timing specification.

28. The method of claim 27, further comprising:

the device operating after said configuring, wherein the device operating comprises the configured hardware element in the device executing to perform the function, and wherein the configured hardware element operates according to the timing specification.

29. A system, comprising:

a computer system comprising a processor, memory and a display; and

a device coupled to the computer system, wherein the device includes a programmable hardware element;

wherein the memory stores a graphical program implementing a function, wherein the graphical program includes a block diagram, and wherein the block diagram includes a timing specification visually depicted in the block diagram specifying timing information of the block diagram;

wherein the memory further stores program instructions executable by the processor to;

generate a hardware description based on the block diagram, wherein the hardware description describes a hardware implementation of the block diagram, wherein the hardware description incorporates the timing specification; and

configure the programmable hardware element in the device utilizing the hardware description to produce a configured hardware element, wherein the configured hardware element implements a hardware implementation of the block diagram, wherein the configured hardware element is configured to operate according to the timing specification.

30. The system of claim 29, wherein the graphical program is a data flow diagram.

31. A system for configuring a device, wherein the device includes a programmable hardware element, the system comprising:

means for creating a block diagram, wherein the block diagram specifies a function, wherein the block diagram includes a timing specification visually depicted in the block diagram;

means for generating a hardware description based on the block diagram, wherein the hardware description describes a hardware implementation of the block diagram, wherein the hardware description incorporates the timing specification; and

means for configuring the programmable hardware element in the device utilizing the hardware description to produce a configured hardware element, wherein the configured hardware element implements a hardware implementation of the block diagram, wherein the configured hardware element is configured to operate according to the timing specification.

32. A memory medium which stores program instructions for configuring a device, wherein the device includes a programmable hardware element, wherein the program instructions are executable by a processor to perform:

storing a graphical program, wherein the graphical program specifies a function, wherein the graphical program comprises a plurality of interconnected nodes which visually indicate functionality of the graphical program;

wherein the graphical program comprises a timing specification visually depicted in the graphical program specifying timing information of one or more of the nodes in the graphical program;

generating a hardware description based on the graphical program, wherein the hardware description describes a hardware implementation of the graphical program, wherein the hardware description incorporates the timing specification; and

configuring the programmable hardware element in the device utilizing the hardware description, wherein after said configuring the programmable hardware element implements a hardware implementation of the graphical program, wherein after said configuring the programmable hardware element is operable to perform the function according to the timing specification.